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* AVR(R) 8 * RISC
- 133 - - 32 x 8 + - - 16 MHz 16 MIPS - - 128K Flash : 10,000 / - - - - 4K EEPROM : 100,000 / - 4K SRAM - 64K - - SPI JTAG ( IEEE 1149.1 ) - JTAG - - JTAG Flash, EEPROM, - 8 / - 16 / - - 8 PWM - 6 2 16 PWM - - 8 10 ADC 8 7 2 1x, 10x, 200x - - USART - / SPI - - - - RC - / - 6 : ADC Standby Standby - - ATmega103 - I/O - 53 I/O - 64 TQFP 64 MLF - 2.7 - 5.5V ATmega128L - 4.5 - 5.5V ATmega128 - 0 - 8 MHz ATmega128L - 0 - 16 MHz ATmega128
*
8 128K Flash ATmega128 ATmega128L
*
*
*
* * *
Rev. 2467L-AVR-05/04
Figure 1. ATmega128
AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2)
ATmega128AVR RISC8CMOS ATmega128 1 MIPS/MHz
2
ATmega128
2467L-AVR-05/04
(OC2/OC1C) PB7 TOSC2/PG3 TOSC1/1PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1(RD) PG0(WR)
ATmega128
Figure 2.
PF0 - PF7
PA0 - PA7
PC0 - PC7
VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS
DATA REGISTER PORTF
DATA DIR. REG. PORTF
DATA REGISTER PORTA
DATA DIR. REG. PORTA
DATA REGISTER PORTC
DATA DIR. REG. PORTC
8-BIT DATA BUS
AVCC AGND AREF PROGRAM COUNTER STACK POINTER WATCHDOG TIMER ADC INTERNAL OSCILLATOR
CALIB. OSC
OSCILLATOR JTAG TAP
OSCILLATOR
ON-CHIP DEBUG
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
TIMING AND CONTROL
BOUNDARYSCAN
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
PEN
PROGRAMMING LOGIC
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
ALU
EEPROM
STATUS REGISTER
USART0
SPI
USART1
TWO-WIRE SERIAL INTERFACE
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
DATA REG. PORTG
DATA DIR. REG. PORTG
+ -
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
RESET
XTAL1
XTAL2
3
2467L-AVR-05/04
AVR 32 (ALU) 10 ATmega128 128K Flash( RWW) 4K EEPROM 4K SRAM 53 I/O 32 RTC4 PWM / (T/C) USART TWI 8 10 ADC( ) SPI IEEE 1149.1 JTAG ( ) CPU SRAM T/C SPI ADC CPU I/O ADC ADC Standby Standby Atmel ISP Flash SPI Flash FlashFlash RWW 8 RISC CPU Flash ATmega128 ATmega128 AVR C /
ATmega103 ATmega128
ATmega128 I/O AVR 64 I/O ATmega103 ATmega103 I/O ATmega128 I/O I/O $60 $FF ( ATmega103 RAM ) LD/LDS/LDD ST/STS/STD IN/OUT ATmega103 RAM ATmega128 M103C ATmega128 ATmega103 I/O RAM ATmega103 ATmega128 ATmega103 PCB ATmega103 "Replacing ATmega103 by ATmega128" ATmega128 ATmega103
ATmega103
M103C RAM I/O ATmega128 ATmega103 ATmega128 * * * * * * * * USART 8 16 / 16 / C G I/O F ADC RC
4
ATmega128
2467L-AVR-05/04
ATmega128
* I/O MCUCSR EXTRF PORF 3 - 0 USART FIFO
ATmega128 ATmega103 * * * *
ATmega103 I/O 0
VCC GND A(PA7..PA0) A 8 I/O A A P 68 B(PB7..PB0) B 8 I/O B B P 69 C(PC7..PC0) C 8 I/O C C P 72 ATmega103 C D(PD7..PD0) D 8 I/O D D P 73 E(PE7..PE0) E 8 I/O E E P 75 F(PF7..PF0) F ADC ADC F 8 I/O F JTAG PF7(TDI) PF5(TMS) PF4(TCK) F JTAG 5
2467L-AVR-05/04
ATmega103 F G(PG4..PG0) G 5 I/O G G ATmega103 G 32 kHz PG0 = 1 PG1 = 1 PG2 = 0 PG3 PG4 RESET XTAL1 XTAL2 AVCC AREF PEN P 47Table 19 ADC AVCC F ADC VCC ADC VCC AREF ADC PENSPI PENSPI PEN C C
6
ATmega128
2467L-AVR-05/04
ATmega128
AVR CPU

AVR CPU Figure 3. AVR
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
AVR Harvard CPU ( ) FLASH 32 8 ALU ALU 6 3 16 16 X Y Z ALU ALU / 16 16 32 / SPM
7
2467L-AVR-05/04
(PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O 64 $20 - $5F ATmega128 SRAM I/O $60 - $FF ST/STS/STD LD/LDS/LDD
ALU
AVR ALU 32 ALU ALU 3 / ALU AVR - SREG -
Bit / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: I I RETI I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N
V
S N 2 V * Bit 3 - V: 2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C:
8
ATmega128
2467L-AVR-05/04
ATmega128
AVR RISC / * * * * 8 8 8 8 8 16 16 16
Figure 4 CPU 32 Figure 4. AVR CPU
7 R0 R1 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X X Y Y Z Z $0D $0E $0F $10 $11 0 Addr. $00 $01 $02
Figure 4 32 SRAM X Y Z X ,Y Z R26..R31 Figure 5 Figure 5. X Y Z
15 X 7 R27 ($1B) XH 0 7 R26 ($1A) XL 0 0
15 Y 7 R29 ($1D)
YH 0 7 R28 ($1C)
YL
0 0
15
ZH
ZL
0
9
2467L-AVR-05/04
Z
7 R31 ($1F)
0
7 R30 ($1E)
0
10
ATmega128
2467L-AVR-05/04
ATmega128
/ AVR SRAM $60 PUSH POP RET RETI AVRI/O8 AVR SPL SPH
Bit 15 SP15 SP7 7 / R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
RAM Z RAMPZ
Bit /
7 - R 0
6 -- R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 RAMPZ0 R/W 0 RAMPZ
* Bits 7..2 - Res: 0 * Bit 1 - RAMPZ0: RAM Z RAMPZ Z 64K RAM ATmega128 64K RAMPZ ELPM/SPM RAMPZ0 RAMPZ0 = 0: RAMPZ0 = 1: ELPM/SPM $0000 - $7FFF ( 64K ) ELPM/SPM $8000 - $FFFF ( 64K )
LPM RAMPZ
AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / /
11
2467L-AVR-05/04
Figure 6.
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 7 ALU Figure 7. ALU
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
AVR I PC BLB02 BLB12 P 267" " P 55" " RESET INT0 - 0 MCU (MCUCR)IVSEL FlashP 55"" BOOTRST Flash P 255" - (RWW, Read-While-Write) " I I RETI I "1" "0" I AVR
12
ATmega128
2467L-AVR-05/04
ATmega128
CLI CLI CLI EEPROM
in cli r16, SREG ; ; EEPROM ; SREG (I-bit) ; SREG
sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16
C
char cSREG; cSREG = SREG; /* */ _CLI(); EECR |= (1<13
2467L-AVR-05/04
SEI
sei ; sleep ; ; :
C
_SEI(); /* */ _SLEEP(); /* */ /* : */
AVR 4 4 4 PC 3 MCU MCU 8 4 PC( ) SREG I
14
ATmega128
2467L-AVR-05/04
ATmega128
AVR ATmega128
ATmega128 AVR ATmega128 EEPROM
Flash ATmega128128KFlash AVR1632 FLASH 64K x 16 Flash
Flash10,000 ATmega128PC16 64K P 255" - (RWW, Read-While-Write) " P 267" " SPI JTAG Flash ( LPM - ELPM - ) P 11" " Figure 8.
Program Memory $0000
Application Flash Section
Boot Flash Section $FFFF
SRAM
ATmega128 SRAM Table 1 Table 1.
ATmega103 SRAM 4096 4000 SRAM 64K 64K
Figure 9 ATmega128 SRAM ATmega128 64I/O(IN/OUT ) I/O $60 - $FF ST/STS/STD
15
2467L-AVR-05/04
LD/LDS/LDD ATmega128 ATmega103 I/O 4352 I/O I/O SRAM 32 64 I/O 160 I/O 4096 SRAM ATmega103 4096 I/O SRAM 32 64 I/O 4000 SRAM ATmega128 64K SRAM SRAM I/O I/O SRAM 4352ATmega1034096(I/O) 61184 ATmega103 61440 P 23" " SRAM SRAM MCU SRAM SRAM / (PG0 PG1) SRAM MCUCR SRE SRAM LD ST LDS STS LDDSTDPUSH POP SRAM SRAM 1 2 3 234 5 7 9 5 R26 R31 Y Z 63 X Y Z 32 I/O 64 4096 SRAM P 9" "
16
ATmega128
2467L-AVR-05/04
ATmega128
Figure 9.
Memory Configuration A
Data Memory
32 Registers 64 I/O Registers 160 Ext I/O Reg. Internal SRAM (4096 x 8) $10FF $1100 External SRAM (0 - 64K x 8) External SRAM (0 - 64K x 8) $0000 - $001F $0020 - $005F $0060 - $00FF $0100
Memory Configuration B
Data Memory
32 Registers 64 I/O Registers Internal SRAM (4000 x 8) $0FFF $1000 $0000 - $001F $0020 - $005F $0060
$FFFF
$FFFF
17
2467L-AVR-05/04
Figure 10 SRAM clkCPU Figure 10. SRAM
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory access instruction
Next instruction
EEPROM
ATmega1284KEEPROM EEPROM 100,000 EEPROM SPI JTAG EEPROM P 267" "
EEPROM /
EEPROM I/O EEPROM Table 2 EEPROM / VCC / CPU P 22 " EEPROM " EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2
EEPROM EEARH EEARL
Bit
15 - EEAR7 7
14 - EEAR6 6 R R/W 0 X
13 - EEAR5 5 R R/W 0 X
12 - EEAR4 4 R R/W 0 X
11 EEAR11 EEAR3 3 R/W R/W X X
10 EEAR10 EEAR2 2 R/W R/W X X
Read
Write
9 EEAR9 EEAR1 1 R/W R/W X X
8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
/
R R/W 0 X
* Bits 15..12 - Res: 0 * Bits 11..0 - EEAR11..0: EEPROM EEARH EEARL 4K EEPROM EEPROM 0 4096 EEAR EEPROM EEPROM EEDR
Bit 7 6 5 4 3 2 1 0
18
ATmega128
2467L-AVR-05/04
ATmega128
MSB / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 LSB R/W 0 EEDR
* Bits 7..0 - EEDR7.0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM EECR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W X 0 EERE R/W 0 EECR
* Bits 7..4 - Res: * Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * Bit 2 - EEMWE: EEPROM EEMWEEEWE"1"EEPROM EEMWE"1" 4 EEWE EEPROM EEMWE "0" EEWE EEMWE 4 * Bit 1 - EEWE: EEPROM EEPROM EEWE EEPROM EEMWE EEPROM (34 ) 1. EEWE 0 2. SPMCSR SPMEN 3. EEPROM EEAR 4. EEPROM EEDR 5. EECR EEMWE "1" EEWE 6. EEMWE 4 EEWE CPU Flash EEPROM EEPROM Flash CPU Flash CPU Flash P 255" - (RWW, Read-While-Write) " : 5 6 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I EEWE EEWE CPU * Bit 0 - EERE: EEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4
19
2467L-AVR-05/04
EEPROM EEWE EEPROM EEAR EEPROM Table 2 CPU EEPROM Table 2. EEPROM
EEPROM ( CPU) Note: RC (1) 8448 8.5 ms
1. 1 MHz CKSEL
20
ATmega128
2467L-AVR-05/04
ATmega128
C EEPROM EEPROM SPM
EEPROM_write: ; sbic EECR,EEWE rjmp EEPROM_write ; (r18:r17) out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE
; (r16) ; EEMWE ; EEWE
C
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* */ while(EECR & (1<21
2467L-AVR-05/04
C EEPROM
EEPROM_read: ; sbic EECR,EEWE rjmp EEPROM_read ; (r18:r17) out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; EERE ;
C
unsigned char EEPROM_read(unsigned int uiAddress) { /* */ while(EECR & (1< EEPROM EEPROM
EEPROM EEPROM EEPROM CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD
I/O
ATmega128 I/O P 342" " ATmega128 I/O I/O I/O LD/LDS/LDDST/STS/STD 32I/O $00 - $1F I/O SBI CBI SBIS SBIC IN OUT $00 - $3F SRAM LD ST I/O $20 ATmega128
22
ATmega128
2467L-AVR-05/04
ATmega128
64 I/O( IN/OUT ) I/O $60 - $FF ST/STS/STD LD/LDS/LDD ATmega128 ATmega103 I/O SRAM "0" I/O "1" CBI SBI I/O "1" CBI SBI $00 to $1F I/O
SRAM Flash LCD A/D D/A * * * * ( )
(XMEM) ( P 2Figure 1 P 68Table 27 P 72Table 33 P 79Table 45 ) Figure 11 Figure 11.
Memory Configuration A 0x0000 Memory Configuration B 0x0000
Internal memory
Internal memory 0x0FFF 0x1000 0x10FF 0x1100
Lower sector SRW01 SRW00 SRW10 External Memory (0-60K x 8)
SRL[2..0] External Memory (0-60K x 8) Upper sector
SRW11 SRW10
0xFFFF
0xFFFF
Note:
ATmega128 ATmega103 A ATmega128 ATmega103 B
ATmega103
(XMCRA XMCRB) I/O ATmega103
23
2467L-AVR-05/04
ATmega103 ATmega103 ATmega103 * * * * * (SRW1n = 0b00 SRW1n = 0b01) RD WR ALE (ATmega128 G)
* * * * * AD7:0 A15:8 ( ) ALE RD WR
3 MCU - MCUCR A - XMCRA B - XMCRB XMEM XMEM P 61"I/O " XMEM XMEM Figure 13 ( ) ALE AD7:0 ALE XMEM ALE RD WR XMEM SRAM SRAMFigure 12 8 SRAM AVR XRAM 8 MHz @ 4V 4 MHz @ 2.7V 74HC XRAM74AHC * * * D Q (tPD) G (tSU) G ( ) (tTH)
XRAM G th = 5 ns Tables 137~Tables 144" " tLAXX_LD/tLLAXX_ST D Q tPD G tSUALE(tAVLLC)PCB( )
24
ATmega128
2467L-AVR-05/04
ATmega128
Figure 12. AVR SRAM
D[7:0] AD7:0 ALE D G Q A[7:0]
AVR
A15:8 RD WR
SRAM
A[15:8] RD WR
25
2467L-AVR-05/04
PORTx "1" AD7:0 PORTx "0" XMEM AD7:0 P 29" B XMCRB" AD7:0 XMEM AD7:0
ATmega128 XMEM 4 Table 4 ATmega128 / ALE ( Tables 137 Tables 144tLLRL+ tRLRH - tDVRH) XMEM XMEM P 308" " Table 137 Table 144 Figure 156 Figure 159 XMEM (XTAL1) XMEM Figure 13. (SRWn1=0 SRWn0=0)
T1 T2 T3 T4
System Clock (CLKCPU )
ALE
A15:8
Prev. addr.
Address
DA7:0
Prev. data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. data
Address
Data
DA7:0 (XMBK = 1)
Prev. data
Address
XXXXX
Data
XXXXXXXX
RD
Note:
1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T4 ALE RAM( )
26
ATmega128
2467L-AVR-05/04
Read
Write
ATmega128
Figure 14. SRWn1 = 0 SRWn0 = 1 (1)
T1 T2 T3 T4 T5
System Clock (CLKCPU )
ALE
A15:8
Prev. addr.
Address
DA7:0
Prev. data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. data
Address
Data
DA7:0 (XMBK = 1)
Prev. data
Address
Data
RD
Note:
1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T5 ALE RAM( )
Figure 15. SRWn1 = 1 SRWn0 = 0 (1)
T1 T2 T3 T4 T5 T6
System Clock (CLKCPU )
ALE
A15:8
Prev. addr.
Address
Read
Write
DA7:0
Prev. data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. data
Address
Data
DA7:0 (XMBK = 1)
Prev. data
Address
Data
RD
Note:
1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T6 ALE RAM( )
27
2467L-AVR-05/04
Read
Write
Figure 16. SRWn1 = 1 SRWn0 = 1 (1)
T1 T2 T3 T4 T5 T6 T7
System Clock (CLKCPU )
ALE
A15:8
Prev. addr.
Address
DA7:0
Prev. data
Address
XX
Data
WR
DA7:0 (XMBK = 0)
Prev. data
Address
Data
DA7:0 (XMBK = 1)
Prev. data
Address
Data
RD
Note:
1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T7 ALE RAM( )
XMEM MCU MCUCR
Bit / 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 SM2 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* Bit 7 - SRE: SRAM/XMEM SRE "1" AD7:0 A15:8 ALE WR RD SRE SRAM I/O * Bit 6 - SRW10: ATmega103 SRWn (XMCRA ) ATmega103 SRW10"1" Figure 14/ A XMCRA
Bit /
7 - R 0
6 SRL2 R/W 0
5 SRL1 R/W 0
4 SRL0 R/W 0
3 SRW01 R/W 0
2 SRW00 R/W 0
1 SRW11 R/W 0
0 - R 0 XMCRA
* Bit 7 - Res: 0 * Bit 6..4 - SRL2, SRL1, SRL0: SRL2 SRL1 SRL0
28
ATmega128
2467L-AVR-05/04
Read
Write
ATmega128
Table 3 Figure 11 SRL2 SRL1 SRL0 0 SRW11 SRW10 Table 3. SRL2..0
SRL2 0 0 0 0 1 1 1 1 SRL1 0 0 1 1 0 0 1 1 SRL0 0 1 0 1 0 1 0 1 = N/A = 0x1100 - 0xFFFF = 0x1100 - 0x1FFF = 0x2000 - 0xFFFF = 0x1100 - 0x3FFF = 0x4000 - 0xFFFF = 0x1100 - 0x5FFF = 0x6000 - 0xFFFF = 0x1100 - 0x7FFF = 0x8000 - 0xFFFF = 0x1100 - 0x9FFF = 0xA000 - 0xFFFF = 0x1100 - 0xBFFF = 0xC000 - 0xFFFF = 0x1100 - 0xDFFF = 0xE000 - 0xFFFF
* Bit 1 MCUCR Bit 6 - SRW11, SRW10: SRW11 SRW10 Table 4 * Bit 3..2 - SRW01, SRW00: SRW01 SRW00 Table 4 Table 4. (1)
SRWn1 0 0 1 1 Note: SRWn0 0 1 0 / /
1 / 1. n = 0 1 ( / ) Figures 13~Figures 16 SRW
* Bit 0 - Res: 0 B XMCRB
Bit /
7 XMBK R/W 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 XMM2 R/W 0
1 XMM1 R/W 0
0 XMM0 R/W 0 XMCRB
* Bit 7- XMBK: XMBK"1"AD7:0 AD7:0 XMEM XMBK
29
2467L-AVR-05/04
XMBKSRE XMEM XMBK"1" * Bit 6..4 - Res: 0 * Bit 2..0 - XMM2, XMM1, XMM0: C 60KB C I/O Table 5 P 32" 64KB " XMMn 64KB Table 5. C
XMM2 0 0 0 0 1 1 1 1 XMM1 0 0 1 1 0 0 1 1 XMM0 0 1 0 1 0 1 0 1 8 ( 60 KB ) 7 6 5 4 3 2 PC7 PC7 - PC6 PC7 - PC5 PC7 - PC4 PC7 - PC3 PC7 - PC2 C
( 64KB)
Figure 11 4,352 4,352 ( 0x0000 ~ 0x10FF) 64 KB 32 KB 0x8000~0x90FF A15 0x8000~0x90FF 0x0000 ~ 0x10FF 0x90FF 32 KB 0x1100~0x90FF 32 KB Figure 17 B ATmega103 A ATmega103 ATmega103 4,096 4,096 0x8000~0x8FFF 32 KB 0x1000~0x8FFF
30
ATmega128
2467L-AVR-05/04
ATmega128
Figure 17. 32 KB
Memory Configuration A
AVR Memory Map External 32K SRAM
Memory Configuration B
AVR Memory Map External 32K SRAM
0x0000 Internal Memory 0x10FF 0x1100
0x0000
0x0000 0x0FFF 0x1000 Internal Memory
0x0000 0x0FFF 0x1000
0x10FF 0x1100
0x7FFF 0x8000
External Memory
0x7FFF
0x7FFF 0x8000
External Memory
0x7FFF
0x90FF 0x9100
0x8FFF 0x9000
(Unused)
(Unused)
0xFFFF
0xFFFF
31
2467L-AVR-05/04
64KB
Figure 11 MCU 60KB ( 0x0000 ~ 0x10FF ) 64KB C 0x00 0x0000 - 0x1FFF (1)
; OFFSET 0x2000 ; C ( ) 0x00 ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; PC7:5 ldi r16, (1<C (1)
#define OFFSET 0x2000 void XRAM_example(void) { unsigned char *p = (unsigned char *) (OFFSET + 1); DDRC = 0xFF; PORTC = 0x00; XMCRB = (1<Note:
1.
32
ATmega128
2467L-AVR-05/04
ATmega128
Figure 18AVR P 41" " . Figure 18.
Asynchronous Timer/Counter General I/O modules ADC CPU Core RAM Flash and EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
AVR Clock Control Unit
Reset Logic
Watchdog Timer
Source clock Clock Multiplexer
Watchdog clock Watchdog Oscillator
Timer/Counter Oscillator
External RC Oscillator
External clock
Crystal Oscillator
Low-Frequency Crystal Oscillator
Calibrated RC Oscillator
CPU clkCPU I/O clkI/O
CPUAVR CPU I/O I/O / SPI USART I/O I/O TWI clkI/O Flash Flash CPU / 32 kHz / ADC ADCCPUI/O ADC
Flash clkFLASH clkASY ADC clkADC
33
2467L-AVR-05/04
AVR Table 6.
/ RC RC Note: 1. "1" "0" CKSEL3..0(1) 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000
CPU CPU WDT Table 7 P 313"ATmega128 " Table 7.
(VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K (65,536)
CKSEL = "0001" SUT = "10" RC
34
ATmega128
2467L-AVR-05/04
ATmega128
XTAL1 XTAL2 Figure 19 CKOPT CKOPT XTAL2 CKOPT CKOPT 8 MHz CKOPT 16 MHz C1 C2 Table 8 Figure 19.
C2 C1
XTAL2 XTAL1 GND
CKSEL3..1 Table 8 Table 8.
CKOPT 1 1 1 0 Note: CKSEL3..1 101
(1)
(MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 1.0 -
C1 C2 - 12 pF - 22 pF 12 pF - 22 pF 12 pF - 22 pF
110 111 101, 110, 111
1.
Table 9 CKSEL0 SUT1..0
35
2467L-AVR-05/04
Table 9.
258 CK
(1)
CKSEL0 0 0 0 0 1 1 1 1 Notes:
SUT1..0 00 01 10 11 00 01 10 11
(VCC = 5.0V) 4.1 ms 65 ms - 4.1 ms 65 ms - 4.1 ms 65 ms
BOD BOD
258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK
1. 2.
32.768 kHz CKSEL "1001" Figure 19 CKOPT XTAL1 XTAL2 36 pF SUT Table 10 Table 10.
SUT1..0 00 01 10 11 Note: 1K CK 1K CK
(1) (1)
(VCC = 5.0V) 4.1 ms 65 ms 65 ms
BOD
32K CK
1.
RC
Figure 20 RC f = 1/(3RC) C 22 pF CKOPT XTAL1GND 36 pF R C RC
36
ATmega128
2467L-AVR-05/04
ATmega128
Figure 20. RC
VCC NC
R
XTAL2 XTAL1
C GND
CKSEL3..0 Table 11 Table 11. RC
CKSEL3..0 0101 0110 0111 1000 (MHz) - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0
SUT Table 12 Table 12. RC
SUT1..0 00 01 10 11 Note: 18 CK 18 CK 18 CK 6 CK(1) (VCC = 5.0V) - 4.1 ms 65 ms 4.1 ms BOD BOD
1.
37
2467L-AVR-05/04
RC
RC 1.0 2.0 4.0 8.0 MHz 5V 25C Table 13 CKSEL (CKOPT) OSCCAL RC 5V 25C 1.0 MHz 3% www.atmel.com/avr 1% P 270" " Table 13. RC
CKSEL3..0 0001(1) 0010 0011 0100 Note: 1. (MHz) 1.0 2.0 4.0 8.0
SUT Table 14 XTAL1 XTAL2 (NC) Table 14. RC
SUT1..0 00 01 10
(1)
6 CK 6 CK 6 CK
(VCC = 5.0V) - 4.1 ms 65 ms
BOD
11 Note: 1.
OSCCAL
Bit / 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL
Note:
ATmega103 OSCCAL
* Bits 7..0 - CAL7..0: 1 MHz ( 0x00) OSCCAL RC Flash EEPROM OSCCAL OSCCAL $FF EEPROM Flash EEPROM Flash
38
ATmega128
2467L-AVR-05/04
ATmega128
10% 1.02.04.0 8.0 MHz Table 15. Table 15. RC
OSCCAL $00 $7F $FF (%) 50 75 100 (%) 100 150 200
XTAL1 Figure 21 CKSEL"0000" CKOPT XTAL1 GND 36 pF Figure 21.
EXTERNAL CLOCK SIGNAL
SUT Table 16 Table 16.
SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD
MCU 2% MCU
39
2467L-AVR-05/04
/
/ (TOSC1 TOSC2) AVR 32.768 kHz TOSC1 XTAL 2 - 129
Bit / 7 XDIVEN R/W 0 6 XDIV6 R/W 0 5 XDIV5 R/W 0 4 XDIV4 R/W 0 3 XDIV3 R/W 0 2 XDIV2 R/W 0 1 XDIV1 R/W 0 0 XDIV0 R/W 0 XDIV
XTAL XDIV
* Bit 7 - XDIVEN: XTAL XDIVEN "1" CPU (clkI/O ADC CPU FLASH) XDIV6 clk clk clk - XDIV0 * Bits 6..0 - XDIV6..XDIV0: XTAL 6 - 0 XDIV6 - XDIV0 d CPU fCLK Source clock f CLK = --------------------------------129 - d XDIVEN XDIVEN"1" XDIV6..XDIV0 MCU
Note: /0 / /
40
ATmega128
2467L-AVR-05/04
ATmega128
MCU AVR MCUCR SE SLEEP ( ADC Standby Standby ) MCUCR SM2 SM1 SM0 Table 17 MCU 4 MCU SLEEP SRAM MCU P 33Figure 18 ATmega128 MCU MCUCR MCU
Bit / 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 SM2 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* Bit 5 - SE: MCU SLEEP SE SLEEP SE SE * Bits 4..2 - SM2..0: Table 17 Table 17.
SM2 0 0 0 0 1 1 1 1 Note: SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 ADC Standby (1) Standby (1)
1. Standby Standby
41
2467L-AVR-05/04
SM2..0 000 SLEEP MCU CPU SPI USART ADC / clkCPU clkFLASH MCU MCU ACSR ACD ADC
ADC
SM2..0 001 SLEEP MCU CPU ADC / 0 clkI/O clkCPU clkFLASH ADC ADC AD ADC BOD / 0 SPM/EEPROM INT7:4 INT3:0 MCU ADC
SM2..0 010 SLEEP MCU BOD INT7:4 INT3:0 MCU MCU P 84" " CKSEL P 34" "
SM2..0 011 SLEEP MCU / 0 ASSR AS0 / 0 / 0 MCU TIMSK SREG I AS0 0 MCU clkASY
Standby
SM2..0 110 SLEEP MCU Standby 6
42
ATmega128
2467L-AVR-05/04
ATmega128
Standby
SM2..0 111 SLEEP MCU Standby 6
Table 18.
ADC Standby (1) Standby (1) Notes: 1. 2. ASSR AS0 3. INT3:0 INT7:4 X(2) X
(2)
X X TWI INT7:0 X(2) X(2) X X(3) X(3) X X X(2)
(2)

clkCPU clkFLASH clkIO clkADC clkASY X X X X X
0
SPM/E2 ADC I/O X X X X X
X X X X X
X X
X
(3)
X(2)
X(3) X(3)
X
X
X(2)
43
2467L-AVR-05/04
AVR ADC ADC P 213" " ADC P 210" " BOD BODEN BOD P 44" " BOD BOD ADC P 50" " P 51" " I/O clkI/O ADC clkADC P 65" " VCC/2

44
ATmega128
2467L-AVR-05/04
ATmega128
JTAG OCDEN * * * OCDEN JTAGEN MCUCSR JTD 1
JTAG JTAG TAP TDO TDO TDI MCUCSR JTD 1 JTAG JTAG
45
2467L-AVR-05/04
AVR I/O JMP Figure 22 Table 19 I/O MCU CKSEL P 34" " ATmega128 5 * * * * * (VPOT) MCU RESET MCU (VBOT) MCU JTAG AVR 1 MCU P 235"IEEE 1149.1 (JTAG) "
Figure 22.
DATA BUS
PEN
D L
Q Q
MCU Control and Status Register (MCUCSR) PORF BORF EXTRF WDRF JTRF Brown-Out Reset Circuit Reset Circuit
Pull-up Resistor Power-On Reset Circuit
BODEN BODLEVEL Pull-up Resistor RESET
SPIKE FILTER
JTAG Reset Register
Watchdog Timer
Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
46
ATmega128
2467L-AVR-05/04
COUNTER RESET
ATmega128
Table 19.
( ) ( )(1) RESET RESET
(2)
1.4 1.3
2.3 2.3 0.85 VCC
V V V s
VPOT
VRST tRST VBOT tBOD VHYST Notes:
0.2 VCC 1.5 BODLEVEL = 1 BODLEVEL = 0 2.4 3.7 2.6 4.0 2 2 100
2.9 4.5
V s s mV

BODLEVEL = 1 BODLEVEL = 0
1. VPOT 2. VBOT VCC = VBOT VCC ATmega128L BODLEVEL=1 ATmega128 BODLEVEL=0 BODLEVEL=1 ATmega128
(POR) Table 19 POR VCC POR POR CC V VCC RESET Figure 23. MCU RESET VCC.
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
47
2467L-AVR-05/04
Figure 24. MCU RESET
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
RESET ( Table 19) VRST( ) tTOUT MCU Figure 25.
CC
ATmega128 BOD(Brown-out Detection) VCC BODLEVEL BOD 2.7V (BODLEVEL ) 4.0V (BODLEVEL ) VBOT+ = VBOT + VHYST/2 VBOT= VBOT - VHYST/2 BOD BODEN BOD(BODEN) VCC (VBOT- Figure 26) BOD VCC (VBOT+ Figure 26) tTOUT MCU VCC Table 19 tBOD BOD
48
ATmega128
2467L-AVR-05/04
ATmega128
Figure 26.
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
49
2467L-AVR-05/04
1 CK tTOUT Figure 27.
CC
CK
MCU MCUCSR
MCU MCU
Bit / 7 JTD R/W 0 6 - R 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUCSR
ATmega103 EXTRF PORF * Bit 4 - JTRF: JTAG JTAG AVR_RESET JTAG MCU JTRF "0" * Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0"
ATmega128 ADC ADC 2.56V Table 20 1. BOD ( BODEN ) 2. (ACSR ACBG ) 3. ADC
50
ATmega128
2467L-AVR-05/04
ATmega128
BOD ACBG ADC Table 20.
VBG tBG IBG 1.15 1.23 40 10 1.40 70 V s A
1 Mhz VCC = 5V VCC P 53Table 22 WDR 8 ATmega128 P 50 M103C WDTON 3 Table 21. 0 ATmega103 P 54" "
51
2467L-AVR-05/04
Table 21. WDT
M103C WDTON 1 2 0 2 WDT WDT
Figure 28.
WATCHDOG OSCILLATOR
WDTCR
Bit /
7 - R 0
6 - R 0
5 - R 0
4 WDCE R/W 0
3 WDE R/W 0
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCR
* Bits 7..5 - Res: * Bit 4 - WDCE: WDE WDCE 4 WDE 1 2 WDCE P 54 " " * Bit 3 - WDE: WDE"1" WDCE"1"WDE 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" 2 P 54 " " * Bits 2..0 - WDP2, WDP1, WDP0: 2, 1, 0
52
ATmega128
2467L-AVR-05/04
ATmega128
WDP2 WDP1 WDP0 Table 22 Table 22.
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 WDT 16K (16,384) 32K (32,768) 64K (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) VCC = 3.0V 14.8 ms 29.6 ms 59.1 ms 0.12 s 0.24 s 0.47 s 0.95 s 1.9 s VCC = 5.0V 14.0 ms 28.1 ms 56.2 ms 0.11 s 0.22 s 0.45 s 0.9 s 1.8 s
53
2467L-AVR-05/04
C WDT ( )
WDT_off: ; WDCE WDE ldi out ldi out ret r16, (1<; WDT
C
void WDT_off(void) { /* WDCE WDE */ WDTCR = (1< 0 ATmega103 WDE WDE WDE ( ) 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" WDP WDCE "0" 2 WDE "1" 1. WDCEWDE"1" WDE "1" 2. 4 WDCE "0" WDP WDE
1
54
ATmega128
2467L-AVR-05/04
ATmega128
ATmega128
Table 23.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (2) $0000(1) $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E $0030(3) $0032 $0034 $0036
(3) (3) (3)
ATmega128 AVR P 12" "
RESET INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMP TIMER0 OVF SPI, STC USART0, RX USART0, UDRE USART0, TX ADC EE READY ANALOG COMP TIMER1 COMPC TIMER3 CAPT TIMER3 COMPA TIMER3 COMPB TIMER3 COMPC TIMER3 OVF USART1, RX
JTAG AVR 0 1 2 3 4 5 6 7 / 2 / 2 / 1 / 1 A / 1 B / 1 / 0 / 0 SPI USART0, Rx USART0 USART0, Tx ADC EEPROM / 1 C / 3 / 3 A / 3 B / 3 C / 3 USART1, Rx
$0038(3) $003A
(3) (3)
$003C
55
2467L-AVR-05/04
Table 23.
32 33 34 35 Notes: (2) $003E(3) $0040(3) $0042
(3) (3)
USART1, UDRE USART1, TX TWI SPM READY
USART1 USART1, Tx
$0044
1. BOOTRST Boot Loader P 255" - (RWW, Read-While-Write) " 2. MCUCRIVSEL Boot Boot 3. $0030 - $0044 ATmega103
Table 24BOOTRST/IVSEL Boot Table 24.
BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 $0000 $0000 Boot Boot $0002 Boot + $0002 $0002 Boot + $0002
Boot P 266Table 112 BOOTRST "0" "1"
56
ATmega128
2467L-AVR-05/04
ATmega128
ATmega128
jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E $0030 $0032 $0034 $0036 $0038 $003A $003C $003E $0040 $0042 $0044 ; $0046 $0047 $0048 $0049 $004A $004B ... ... RESET:ldir16, high(RAMEND); out ldi out sei ... SPH,r16 SPL,r16 ; xxx ... ; RAM r16, low(RAMEND) RESET EXT_INT0 EXT_INT1 EXT_INT2 EXT_INT3 EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 TIM2_COMP TIM2_OVF TIM1_CAPT
; ; IRQ0 ; IRQ1 ; IRQ2 ; IRQ3 ; IRQ4 ; IRQ5 ; IRQ6 ; IRQ7 ; 2 ; 2 ; 1
TIM1_COMPA ; 1 A TIM1_COMPB ; 1 B TIM1_OVF TIM0_COMP TIM0_OVF SPI_STC ; 1 ; 0 ; 0 ; SPI
USART0_RXC ; USART0 USART0_DRE ; USART0,UDR USART0_TXC ; USART0 ADC EE_RDY ANA_COMP TIM3_CAPT ; ADC ; EEPROM ; ; 3
TIM1_COMPC ; 1 C TIM3_COMPA ; 3 A TIM3_COMPB ; 3 B TIM3_COMPC ; 3 C TIM3_OVF ; 3 USART1_RXC ; USART1 USART1_DRE; USART1,UDR USART1_TXC ; USART1 TWI SPM_RDY ; ; SPM
BOOTRST Boot 8K MCUCR IVSEL
$0000 RESET:ldi r16,high(RAMEND) ;
57
2467L-AVR-05/04
$0001 $0002 $0003 $0004 $0005 ; .org $F002 $F002 $F004 ... $F044
out ldi out sei
SPH,r16 SPL,r16
; RAM
r16,low(RAMEND) ; xxx
jmp jmp ... jmp jmp jmp ... jmp
EXT_INT0 EXT_INT1 ... SPM_RDY
; IRQ0 ; IRQ1 ; ; SPM
BOOTRST Boot 8K
.org $0002 $0002 $0004 ... $0044 ; .org $F000 $F000 RESET: ldi $F001 $F002 $F003 $F004 $F005 out ldi out sei r16,high(RAMEND) ; SPH,r16 SPL,r16 ; xxx ; RAM r16,low(RAMEND) EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 ; IRQ1 ; ; SPM
BOOTRST Boot 8K MCUCR IVSEL
; .org $F000 $F000 $F002 $F004 ... $F044 $F046 $F047 $F048 $F049 $F04A $F04B jmp jmp jmp ... jmp RESET: ldi out ldi out sei RESET EXT_INT0 EXT_INT1 ... SPM_RDY SPH,r16 SPL,r16 ; xxx ; Reset ; IRQ0 ; IRQ1 ; ; SPM ; RAM
r16,high(RAMEND) ; r16,low(RAMEND)
Boot MCU MCUCR
Bit /
7 SRE R/W
6 SRW10 R/W
5 SE R/W
4 SM1 R/W
3 SM0 R/W
2 SM2 R/W
1 IVSEL R/W
0 IVCE R/W MCUCR
58
ATmega128
2467L-AVR-05/04
ATmega128
0 0 0 0 0 0 0 0
* Bit 1 - IVSEL: IVSEL "0" Flash IVSEL "1" Boot Boot BOOTSZ P 255" - (RWW, Read-While-Write) " IVSEL : 1. IVCE 4 IVSEL IVCE "0" IVCE IVSEL IVSEL IVCE 4 I
Note: Boot BootBLB02 Boot BLB12 Boot Boot P 255" - (RWW, Read-While-Write) "
59
2467L-AVR-05/04
* Bit 0 - IVCE: IVSEL IVCE IVCE IVSEL 4 IVCE IVCE
Move_interrupts: ; ldi out ldi out ret r16, (1<; boot
C
void Move_interrupts(void) { /* */ MCUCR = (1<60
ATmega128
2467L-AVR-05/04
ATmega128
I/O
I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure 29 P 299" " Figure 29. I/O
RPU
Pxn
Logic CPIN
See Figure "General Digital I/O" for Details
"x" "n" PORTB3 B 3 PORTxn I/O P 81"I/O " I/O - PORTx - DDRx - PINx / SFIOR PUD I/O P 62" I/O " P 66" " I/O
61
2467L-AVR-05/04
I/O
( ) I/O Figure 30 I/O Figure 30. I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx
RDx
Pxn
Q
D
PORTxn Q CLR
WPx RESET SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WPx: RRx: RPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN
Note:
1. WPx, WDx, RRx, RPx RDx I/O, SLEEP clk PUD
DDxn PORTxn PINxn P 81"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0") ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) SFIOR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11)
62
ATmega128
2467L-AVR-05/04
DATA BUS
ATmega128
Table 25 Table 25.
DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD (in SFIOR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( )
DDxn PINxn Figure 30 PINxn Figure 31 tpd,max tpd,min Figure 31.
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 tpd, max tpd, min 0xFF XXX XXX in r17, PINx
SYNC LATCH PINxn tpd,max tpd,min 1/2 ~ 11/2 Figure 32 out in nop out SYNC LATCH tpd
63
2467L-AVR-05/04
Figure 32.
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 tpd 0xFF out PORTx, r16 nop 0xFF
in r17, PINx
64
ATmega128
2467L-AVR-05/04
ATmega128
B 0 1 2 3 4 7 6 7 nop (1)
... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1<; nop
C (1)
unsigned char i; ... /* */ /* */ PORTB = (1<Note:
1.
Figure 30 ( ) SLEEP MCU VCC/2 SLEEP SLEEP P 66" " MCU SLEEP
( ) VCC GND
65
2467L-AVR-05/04
I/O Figure 33 Figure 30 AVR Figure 33. (1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
WPx RESET RRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL
PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RLx, RPxRDx I/O, SLEEP clk PUD
Table 26 Figure 33
66
ATmega128
2467L-AVR-05/04
DATA BUS
ATmega128
Table 26.
PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE PUOV / / DDxnPORTxn PUD DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) /
PUOV
DDOE DDOV PVOE
PVOV DIEOE
DIEOV DI
AIO
/

67
2467L-AVR-05/04
IO SFIOR
Bit / 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR0 R/W 0 0 PSR321 R/W 0 SFIOR
* Bit 2 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P 62" " A A Table 27. A
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 AD7 ( 7) AD6 ( 6) AD5 ( 5) AD4 ( 4) AD3 ( 3) AD2 ( 2) AD1 ( 1) AD0 ( 0)
Table 28 Table 29 A P 66Figure 33 Table 28. PA7..PA4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PA7/AD7 SRE ~(WR | ADA ) * PORTA7 * PUD SRE WR | ADA SRE A7 * ADA | D7 OUTPUT * WR 0 0 D7 -
(1)
PA6/AD6 SRE ~(WR | ADA) * PORTA6 * PUD SRE WR | ADA SRE A6 * ADA | D6 OUTPUT * WR 0 0 D6 -
PA5/AD5 SRE ~(WR | ADA) * PORTA5 * PUD SRE WR | ADA SRE A5 * ADA | D5 OUTPUT * WR 0 0 D5 -
PA4/AD4 SRE ~(WR | ADA) * PORTA4 * PUD SRE WR | ADA SRE A4 * ADA | D4 OUTPUT * WR 0 0 D4 -
1. ADA (ADdress Active) P 23" "
68
ATmega128
2467L-AVR-05/04
ATmega128
Table 29. PA3..PA0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PA3/AD3 SRE ~(WR | ADA) * PORTA3 * PUD SRE WR | ADA SRE A3 * ADA | D3 OUTPUT * WR 0 0 D3 - PA2/AD2 SRE ~(WR | ADA) * PORTA2 * PUD SRE WR | ADA SRE A2* ADA | D2 OUTPUT * WR 0 0 D2 - PA1/AD1 SRE ~(WR | ADA) * PORTA1 * PUD SRE WR | ADA SRE A1 * ADA | D1 OUTPUT * WR 0 0 D1 - PA0/AD0 SRE ~(WR | ADA) * PORTA0 * PUD SRE WR | ADA SRE A0 * ADA | D0 OUTPUT * WR 0 0 D0 -
B
B Table 30 Table 30. B
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Note: T/C1 PWM C) OC2/OC1C(1) (T/C2 PWM OC1B (T/C1 PWM B) OC1A (T/C1 PWM A) OC0 (T/C0 PWM ) MISO (SPI / ) MOSI (SPI / ) SCK (SPI ) SS (SPI ) 1. ATmega103 OC1C
* OC2/OC1C, Bit 7 OC2 PB7 T/C2 (DDB7 "1") OC2 PWM OC1C C PB7 T/C1 C (DDB7 "1") OC1C PWM * OC1B, Bit 6 OC1B B PB6T/C1B (DDB6 "1") OC1B PWM * OC1A, Bit 5 OC1A A PB5T/C1A (DDB5 "1") OC1A PWM 69
2467L-AVR-05/04
* OC0, Bit 4 OC0 PB4 T/C0 (DDB4 "1") OC0 PWM * MISO - B, Bit 3 MISO: SPI DDB3 DDB3 PORTB3 * MOSI - B, Bit 2 MOSI: SPI DDB2 DDB2 PORTB2 * SCK - B, Bit 1 SCK: SPI DDB1 DDB1 PORTB1 * SS - B, Bit 0 SS: DDB0 DDB0 PORTB0 Table 31Table 32 BP 66Figure 33 SPI MSTR INPUTSPI SLAVE OUTPUTMISO MOSISPI MSTR OUTPUT SPI SLAVE INPUT Table 31. PB7..PB4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PB7/OC2/OC1C 0 0 0 0 OC2/OC1C OC2/OC1C(1) 0 0 - -
(1)
PB6/OC1B 0 0 0 0 OC1B OC1B 0 0 - -
PB5/OC1A 0 0 0 0 OC1A OC1A 0 0 - -
PB4/OC0 0 0 0 0 OC0 OC0B 0 0 - -
1. P 145" (OCM1C2)" ATmega103 OC1C
70
ATmega128
2467L-AVR-05/04
ATmega128
Table 32. PB3..PB0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB3/MISO SPE * MSTR PORTB3 * PUD SPE * MSTR 0 SPE * MSTR SPI 0 0 SPI - PB2/MOSI SPE * MSTR PORTB2 * PUD SPE * MSTR 0 SPE * MSTR SPI 0 0 SPI - PB1/SCK SPE * MSTR PORTB1 * PUD SPE * MSTR 0 SPE * MSTR SCK 0 0 SCK - PB0/SS SPE * MSTR PORTB0 * PUD SPE * MSTR 0 0 0 0 0 SPI SS -
71
2467L-AVR-05/04
C
ATmega103 C Table 33. C
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 A15 A14 A13 A12 A11 A10 A9 A8
Table 34 Table 35 C P 66Figure 33 Table 34. PC7..PC4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PC7/A15 SRE * (XMM <1) 0 SRE * (XMM<1) 1 SRE * (XMM<1) A11 0 0 - -
(1)
PC6/A14 SRE * (XMM<2) 0 SRE * (XMM<2) 1 SRE * (XMM<2) A10 0 0 - -
PC5/A13 SRE * (XMM<3) 0 SRE * (XMM<3) 1 SRE * (XMM<3) A9 0 0 - -
PC4/A12 SRE * (XMM<4) 0 SRE * (XMM<4) 1 SRE * (XMM<4) A8 0 0 - -
1. ATmega103 XMM = 0
72
ATmega128
2467L-AVR-05/04
ATmega128
Table 35. PC3..PC0 (1)
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PC3/A11 SRE * (XMM<5) 0 SRE * (XMM<5) 1 SRE * (XMM<5) A11 0 0 - - PC2/A10 SRE * (XMM<6) 0 SRE * (XMM<6) 1 SRE * (XMM<6) A10 0 0 - - PC1/A9 SRE * (XMM<7) 0 SRE * (XMM<7) 1 SRE * (XMM<7) A9 0 0 - - PC0/A8 SRE * (XMM<7) 0 SRE * (XMM<7) 1 SRE * (XMM<7) A8 0 0 - -
1. ATmega103 XMM = 0
D
D Table 36 Table 36. D
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Note: T2 (T/C2 ) T1 (T/C1 ) XCK1(1) (USART1 / ) ICP1 (T/C1 ) INT3/TXD1(1) ( 3 UART1 ) INT2/RXD1(1) ( 2 UART1 ) INT1/SDA(1) ( 1 TWI ) INT0/SCL(1) ( 0 TWI )
1. ATmega103 XCK1 TXD1 RXD1 SDA SCL
* T2 - D, Bit 7 T2 T/C2 * T1 - D, Bit 6 T1 T/C1 * XCK1 - D, Bit 4 XCK1USART1 (DDD4)(DDD4 '0') (DDD4 '1') USART1 XCK1
73
2467L-AVR-05/04
* ICP1 - D, Bit 4 ICP1 - 1 PD4 T/C1 * INT3/TXD1 - D, Bit 3 INT3 3 PD3 MCU TXD1 USART1 USART1 DDD3 * INT2/RXD1 - D, Bit 2 INT2 2 PD2 MCU RXD1 USART1 USART1 DDD2 PORTD2 * INT1/SDA - D, Bit 1 INT1 1 PD1 MCU SDA : TWCR TWEN PD1 I/O 50ns * INT0/SCL - D, Bit 0 INT0 0 PD0 MCU SCL TWCR TWEN PD0 I/O 50ns Table 37 Table 38 D P 66Figure 33 Table 37. PD7..PD4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD7/T2 0 0 0 0 0 0 0 0 T2 - PD6/T1 0 0 0 0 0 0 0 0 T1 - PD5/XCK1 0 0 0 0 UMSEL1 XCK1 0 0 XCK1 - PD4/ICP1 0 0 0 0 0 0 0 0 ICP1 -
74
ATmega128
2467L-AVR-05/04
ATmega128
Table 38. PD3..PD0 (1)
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PD3/INT3/TXD1 TXEN1 0 TXEN1 1 TXEN1 TXD1 INT3 1 INT3 - PD2/INT2/RXD1 RXEN1 PORTD2 * PUD RXEN1 0 0 0 INT2 1 INT2 /RXD1 - PD1/INT1/SDA TWEN PORTD1 * PUD TWEN SDA_OUT TWEN 0 INT1 1 INT1 SDA PD0/INT0/SCL TWEN PORTD0 * PUD TWEN SCL_OUT TWEN 0 INT0 1 INT0 SCL
1. PD0 PD1 AIO TWI
E
E Table 39 Table 39. E
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Note: INT7/IC3(1) ( 7 T/C3 ) INT6/ T3(1) ( 6 T/C3 ) T/C3 PWM C ) INT5/OC3C(1) ( 5 INT4/OC3B(1) ( 4 T/C3 PWM B ) AIN1/OC3A (1) ( T/C3 PWM A ) AIN0/XCK0(1) ( USART0 / ) PDO/TXD0 ( USART0 ) PDI/RXD0 ( USART0 ) 1. ATmega103 ICP3T3OC3COC3BOC3BOC3A XCK0
* INT7/ICP3 - E, Bit 7 INT7 7 PE7 MCU ICP3 - 3 PE7 T/C3 * INT6/T3 - E, Bit 6 INT6 6 PE6 T3 T/C3 * INT5/OC3C - E, Bit 5 INT5 5 PE5 OC3C C PE5 T/C3 C DDE5 OC3C PWM * INT4/OC3B - E, Bit 4
75
2467L-AVR-05/04
INT4 4 PE4 OC3B B PE4 T/C3 B DDE4 OC3B PWM * AIN1/OC3A - E, Bit 3 AIN1 - OC3A A PE3 T/C3 A DDE3 OC3A PWM * AIN0/XCK0 - E, Bit 2 AIN0 - XCK0 USART0 DDE2 (DDE2 '0') (DDE2 '1') USART0 XCK0 * PDO/TXD0 - E, Bit 1 PDO SPI TXD0 UART0 * PDI/RXD0 - E, Bit 0 PDI SPI RXD0 USART0 USART0DDRE0 PORTE0 Table 40 Table 41 E P 66Figure 33 Table 40. PE7..PE4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PE7/INT7/ICP3 0 0 0 0 0 0 INT7 1 INT7 /ICP3 - PE6/INT6/T3 0 0 0 0 0 0 INT6 1 INT7 /T3 - PE5/INT5/OC3C 0 0 0 0 OC3C OC3C INT5 1 INT5 - PE4/INT4/OC3B 0 0 0 0 OC3B OC3B INT4 1 INT4 -
76
ATmega128
2467L-AVR-05/04
ATmega128
Table 41. PE3..PE0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PE3/AIN1/OC3A 0 0 0 0 OC3B OC3B 0 0 0 AIN1 PE2/AIN0/XCK0 0 0 0 0 UMSEL0 XCK0 0 0 XCK0 AIN0 PE1/PDO/TXD0 TXEN0 0 TXEN0 1 TXEN0 TXD0 0 0 - - PE0/PDI/RXD0 RXEN0 PORTE0 * PUD RXEN0 0 0 0 0 0 RXD0 -
F
Table 42 F ADC F AD ATmega103 F JTAG PF7(TDI) PF5(TMS) PF4(TCK) Table 42. F
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ADC7/TDI (ADC 7 JTAG ) ADC6/TDO (AD 6 JTAG ) ADC5/TMS (ADC 5 JTAG ) ADC4/TCK (ADC 4 JTAG ) ADC3 (ADC 3) ADC2 (ADC 2) ADC1 (ADC 1) ADC0 (ADC 0)
* TDI, ADC7 - F, Bit 7 ADC7 7 TDIJTAG ( ) JTAG I/O * TDO, ADC6 - F, Bit 6 ADC6 6 TDOJTAG JTAG I/O TAP TDO * TMS, ADC5 - F, Bit 5 ADC5 5
77
2467L-AVR-05/04
TMS JTAG TAP JTAG I/O * TCK, ADC4 - F, Bit 4 ADC4 4 TCK JTAG JTAG TCK JTAG I/O * ADC3 - ADC0 - F, Bit 3..0 3..0 Table 43. PF7..PF4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PF7/ADC7/TDI JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TDI/ADC7 PF6/ADC6/TDO JTAGEN 0 JTAGEN SHIFT_IR + SHIFT_DR JTAGEN TDO JTAGEN 0 - ADC6 PF5/ADC5/TMS JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TMS/ADC5 PF4/ADC4/TCK JTAGEN 1 JTAGEN 0 0 0 JTAGEN 0 - TCKADC4
Table 44. PF3..PF0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PF3/ADC3 0 0 0 0 0 0 0 0 - ADC3 PF2/ADC2 0 0 0 0 0 0 0 0 - ADC2 PF1/ADC1 0 0 0 0 0 0 0 0 - ADC1 PF0/ADC0 0 0 0 0 0 0 0 0 - ADC0
78
ATmega128
2467L-AVR-05/04
ATmega128
G ATmega103 G Table 45. G
PG4 PG3 PG2 PG1 PG0 TOSC1 (RTC T/C0) TOSC2 (RTC T/C0) ALE ( ) RD ( ) WR ( )
* TOSC1 - G, Bit 4 TOSC1 1 ASSR AS0 T/C0 PG4 I/O * TOSC2 - G, Bit 3 TOSC2 2 ASSR AS0 T/C0 PG3 I/O * ALE - G, Bit 2 ALE * RD - G, Bit 1 RD * WR - G, Bit 0 WR Table 46 Table 47 E P 66Figure 33 Table 46. PG4..PG1
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PG4/TOSC1 AS0 0 AS0 0 0 0 AS0 0 - T/C0 OSC PG3/TOSC2 AS0 0 AS0 0 0 0 AS0 0 - T/C0 OSC PG2/ALE SRE 0 SRE 1 SRE ALE 0 0 - - PG1/RD SRE 0 SRE 1 SRE RD 0 0 - -
79
2467L-AVR-05/04
Table 47. PG0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PG0/WR SRE 0 SRE 1 SRE WR 0 0 - -
80
ATmega128
2467L-AVR-05/04
ATmega128
I/O
A PORTA
Bit / 7
PORTA7
6
PORTA6
5
PORTA5
4
PORTA4
3
PORTA3
2
PORTA2
1
PORTA1
0
PORTA0 PORTA
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
A DDRA
Bit /
7 DDA7 R/W 0
6 DDA6 R/W 0
5 DDA5 R/W 0
4 DDA4 R/W 0
3 DDA3 R/W 0
2 DDA2 R/W 0
1 DDA1 R/W 0
0 DDA0 R/W 0 DDRA
A PINA
Bit /
7 PINA7 R N/A
6 PINA6 R N/A
5 PINA5 R N/A
4 PINA4 R N/A
3 PINA3 R N/A
2 PINA2 R N/A
1 PINA1 R N/A
0 PINA0 R N/A PINA
B PORTB
Bit /
7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
B DDRB
Bit /
7 DDB7 R/W 0
6 DDB6 R/W 0
5 DDB5 R/W 0
4 DDB4 R/W 0
3 DDB3 R/W 0
2 DDB2 R/W 0
1 DDB1 R/W 0
0 DDB0 R/W 0 DDRB
B PINB
Bit /
7 PINB7 R N/A
6 PINB6 R N/A
5 PINB5 R N/A
4 PINB4 R N/A
3 PINB3 R N/A
2 PINB2 R N/A
1 PINB1 R N/A
0 PINB0 R N/A PINB
C PORTC
Bit /
7
PORTC7
6
PORTC6
5
PORTC5
4
PORTC4
3
PORTC3
2
PORTC2
1
PORTC1
0
PORTC0 PORTC
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
C DDRC
Bit /
7 DDC7 R/W 0
6 DDC6 R/W 0
5 DDC5 R/W 0
4 DDC4 R/W 0
3 DDC3 R/W 0
2 DDC2 R/W 0
1 DDC1 R/W 0
0 DDC0 R/W 0 DDRC
81
2467L-AVR-05/04
C PINC
Bit /
7 PINC7 R N/A
6 PINC6 R N/A
5 PINC5 R N/A
4 PINC4 R N/A
3 PINC3 R N/A
2 PINC2 R N/A
1 PINC1 R N/A
0 PINC0 R N/A PINC
ATmega103 DDRC PINC ATmega103 DDRC 100% ATmega103 D PORTD
Bit / 7
PORTD7
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D DDRD
Bit /
7 DDD7 R/W 0
6 DDD6 R/W 0
5 DDD5 R/W 0
4 DDD4 R/W 0
3 DDD3 R/W 0
2 DDD2 R/W 0
1 DDD1 R/W 0
0 DDD0 R/W 0 DDRD
D PIND
Bit /
7 PIND7 R N/A
6 PIND6 R N/A
5 PIND5 R N/A
4 PIND4 R N/A
3 PIND3 R N/A
2 PIND2 R N/A
1 PIND1 R N/A
0 PIND0 R N/A PIND
E PORTE
Bit /
7
PORTE7
6
PORTE6
5
PORTE5
4
PORTE4
3
PORTE3
2
PORTE2
1
PORTE1
0
PORTE0 PORTE
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
E DDRE
Bit /
7 DDE7 R/W 0
6 DDE6 R/W 0
5 DDE5 R/W 0
4 DDE4 R/W 0
3 DDE3 R/W 0
2 DDE2 R/W 0
1 DDE1 R/W 0
0 DDE0 R/W 0 DDRE
E PINE
Bit /
7 PINE7 R N/A
6 PINE6 R N/A
5 PINE5 R N/A
4 PINE4 R N/A
3 PINE3 R N/A
2 PINE2 R N/A
1 PINE1 R N/A
0 PINE0 R N/A PINF
F PORTF
Bit /
7
PORTF7
6
PORTF6
5
PORTF5
4
PORTF4
3
PORTF3
2
PORTF2
1
PORTF1
0
PORTF0 PORTF
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
82
ATmega128
2467L-AVR-05/04
ATmega128
F DDRF
Bit / 7 DDF7 R/W 0 6 DDF6 R/W 0 5 DDF5 R/W 0 4 DDF4 R/W 0 3 DDF3 R/W 0 2 DDF2 R/W 0 1 DDF1 R/W 0 0 DDF0 R/W 0 DDRF
F PINF
Bit /
7 PINF7 R N/A
6 PINF6 R N/A
5 PINF5 R N/A
4 PINF4 R N/A
3 PINF3 R N/A
2 PINF2 R N/A
1 PINF1 R N/A
0 PINF0 R N/A PINF
ATmega103 PORTF DDRF F G PORTG
Bit / 7 - R 0 6 - R 0 5 - R 0 4
PORTG4
3
PORTG3
2
PORTG2
1
PORTG1
0
PORTG0 PORTG
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
G DDRG
Bit /
7 - R 0
6 - R 0
5 - R 0
4 DDG4 R/W 0
3 DDG3 R/W 0
2 DDG2 R/W 0
1 DDG1 R/W 0
0 DDG0 R/W 0 DDRG
G PING
Bit /
7 - R 0
6 - R 0
5 - R 0
4 PING4 R N/A
3 PING3 R N/A
2 PING2 R N/A
1 PING1 R N/A
0 PING0 R N/A PING
ATmega103 PORTG DDRG PING TOSC1 TOSC2 WR RD ALE)
83
2467L-AVR-05/04
INT7:0 INT7:0 - EICRA (INT3:0) EICRB (INT7:4) INT7:4 I/O P 33" " INT3:0 ( ) I/O MCU MCU 5.0V 25C 1 s P 299" " MCU SUT P 33" " MCU MCU
A EICRA
Bit /
7 ISC31 R/W 0
6 ISC30 R/W 0
5 ISC21 R/W 0
4 ISC20 R/W 0
3 ISC11 R/W 0
2 ISC10 R/W 0
1 ISC01 R/W 0
0 ISC00 R/W 0 EICRA
ATmega103 INT3:0 * Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: 3 - 0 3 - 0 INT3:0 SREG I EIMSK Table 48 INT3..INT0 INT3:0 Table 49 ISCn EIMSK INTn ISCn EIFR INTFn '1' Table 48. (1)
ISCn1 0 0 1 1 Note: ISCn0 0 1 0 INTn INTn
1 INTn 1. n =3 2 1 0 ISCn1/ISCn0 EIMSK ISCn1/ISCn0
Table 49. ( )
tINT ( ) 50 ns
B EICRB
Bit
7 ISC71
6 ISC70
5 ISC61
4 ISC60
3 ISC51
2 ISC50
1 ISC41
0 ISC40 EICRB
84
ATmega128
2467L-AVR-05/04
ATmega128
/ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
* Bits 7..0 - ISC71, ISC70 - ISC41, ISC40: 7 - 4 7 - 4 INT7:4 SREG I EIMSK Table 50 MCU INT7:4 ( ) XTAL CPU XTAL Table 50. (1)
ISCn1 0 0 1 1 Note: ISCn0 0 1 0 INTn INTn INTn
1 INTn 1. n = 7 6 5 4 ISCn1/ISCn0 EIMSK ISCn1/ISCn0
EIMSK
Bit / 7 INT7 R/W 0 6 INT6 R/W 0 5 INT5 R/W 0 4 INT4 R/W 0 3 INT3 R/W 0 2 INT2 R/W 0 1 INT1 R/W 0 0 IINT0 R/W 0 EIMSK
* Bits 7..0 - INT7 - INT0: 7 - 0 INT7 - INT0 '1' SREG I - EICRA EICRB EIFR
Bit / 7 INTF7 R/W 0 6 INTF6 R/W 0 5 INTF5 R/W 0 4 INTF4 R/W 0 3 INTF3 R/W 0 2 INTF2 R/W 0 1 INTF1 R/W 0 0 IINTF0 R/W 0 EIFR
* Bits 7..0 - INTF7 - INTF0: 7 - 0 INT7:0 INTF7:0 SREG I EIMSK '1' MCU '1' INT7:0 '0' INTF3:0 P 65" "
85
2467L-AVR-05/04
8 / 0 - PWM
T/C0 8 / * * ( ) * PWM * * 10 * (TOV0 OCF0) * 32kHz Figure 348/ P 2"" CPU I/O I/O P 94"8 T/C " Figure 34. 8 T/C
TCCRn
count clear direction Control Logic
TOVn (Int.Req.) clkTn TOSC1
BOTTOM
TOP Prescaler
T/C Oscillator TOSC2
Timer/Counter TCNTn
=0
= 0xFF
OCn (Int.Req.) clk I/O
=
Waveform Generation
OCn
OCRn
DATABUS
Synchronized Status flags
clk I/O Synchronization Unit clk ASY
Status flags
ASSRn asynchronous mode select (ASn)
T/C(TCNT0)(OCR0)8 TIFR TIMSK TIFR TIMSK T/C TOSC1/2 ASSR T/C clkT0 OCR0 T/C PWM OC0 P 88 "" OCF0
86
ATmega128
2467L-AVR-05/04
ATmega128
"n" T/C 0 ( TCNT0 T/C0 ) Table 51 Table 51. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOP TOP 0xFF (MAX) OCR0
T/C
T/C clkT0 MCU clkI/O ASSR AS0 TOSC1 TOSC2 P 97" ASSR" P 99" / " 8 T/C Figure 35 Figure 35.
DATA BUS
TOVn (Int.Req.) TOSC1 count TCNTn clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC2
bottom
top
clkI/O
( ) count direction clear clkT0 top bottom TCNT0 1 1 TCNT0 ( ) T/C TCNT0 TCNT0 (0)
clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) T/C (TCCR0) WGM01 WGM00 OC0 P 89" " T/CTOV0WGM01:0 TOV0CPU
87
2467L-AVR-05/04
8 TCNT0 OCR0 TCNT0 OCR0 OCF0 OCIE0 = 1 OCF0 '1' WGM01:0COM01:0 max bottom (P 89" " )Figure 36 Figure 36.
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top bottom FOCn
Waveform Generator
OCxy
WGMn1:0
COMn1:0
PWM OCR0 OCR0 top bottom PWM OCR0 CPU OCR0 CPU OCR0 PWM FOC0 '1' OCF0 / OC0 (COM01:0 OC0 ) CPU TCNT0 OCR0 TCNT0 TCNT0 TCNT0 T/C TCNT0OCR0 TCNT0 BOTTOM
TCNT0
88
ATmega128
2467L-AVR-05/04
ATmega128
OC0 OC0 FOC0 OC0 COM01:0 COM01:0
COM01:0 COM01:0 OC0 COM01:0 OC0 Figure 37 COM01:0 I/O I/O I/O COM01:0 I/O (DDR PORT) OC0 OC0 OC0 Figure 37.
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM01:0 OC0 I/O OC0 (DDR) OC0 DDR_OC0 OC0 COM01:0 P 94 "8 T/C " COM01:0 CTC PWM COM01:0 = 0 OC0 PWM P 95Table 53 PWMP 95Table 54 PWM P 96Table 55 COM01:0 PWM FOC0
T/C (WGM01:0) (COM01:0) COM01:0 PWM PWM COM01:0 (P 89 " " ) P 93"T/C "
89
2467L-AVR-05/04
(WGM01:0 = 0) (TOP = 0xFF) 0x00 TCNT0 T/C TOV0 TOV0 9 TOV0 CPU
CTC( )
CTC (WGM01:0 = 2) OCR0 TCNT0 OCR0 OCR0 top CTCFigure 38 TCNT0TCNT0OCR0 TCNT0 Figure 38. CTC
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
OCF0 TOP TOP CTC TOP BOTTOM OCR0 TCNT0 0xFF 0x00 OCR0 COM01:0 = 1 CTC OC0 OC0 fOC0 = fclk_I/O/2 (OCR0 = 0x00) f clk_I/O f OCn = -----------------------------------------------2 N ( 1 + OCRn ) N (1 8 32 64 128 256 1024) TOV0 MAX 0x00 PWM PWM (WGM01:0 = 3) PWM PWM PWM(PWM) BOTTOM MAX BOTTOM OC0 TCNT0 OCR0 BOTTOM OC0 PWM PWM PWM
90
ATmega128
2467L-AVR-05/04
ATmega128
DAC ( ) PWM MAX Figure 39 TCNT0 PWM PWM TCNT0 OCR0 TCNT0 Figure 39. PWM
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
Max T/C TOV0 PWM OC0 PWM COM01:0 2 PWM 3 PWM ( P 95Table 54 ) OC0 PWMOC0 OCR0 TCNT0 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnPWM = -----------------N 256 N (1 8 32 64 128 256 1024) OCR0 PWM OCR0 BOTTOM MAX+1 OCR0 MAX COM01:0 OC0 (COM01:0 = 1) 50% foc0 = fclk_I/O/2 OCR0 0 CTC OC0 PWM
91
2467L-AVR-05/04
PWM
PWM (WGM01:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT0 OCR0 OC0 BOTTOM TCNT0 OCR0 OC0 PWM PWM 8 Max TCNT0 MAX Figure 40 TCNT0 PWM PWM TCNT0 OCR0 TCNT0 Figure 40. PWM
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV0 PWM OC0 PWM COM01:0 2 PWM COM01:0 3 PWM ( P 96Table 55 ) OC0 OCR0 TCNT0 OC0 PWM PWM f clk_I/O f OCnPCPWM = -----------------N 510 N (1 8 32 64 128 256 1024) OCR0 PWM PWM OCR0 BOTTOM OCR0 MAX PWM Figure 40 OCn BOTTOM
92
ATmega128
2467L-AVR-05/04
ATmega128
* Figure 40 OCR0A MAX OCR0A MAX OCn BOTTOM OCn MAX OCR0A OCn
*
T/C
Figure 41 Figure 42 / (T/C) T/C clkT0 MAX Figure 43Figure 44 T/C clkT0 clkI/O T/C Figure 41 T/C PWM MAX Figure 41. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 42 Figure 42. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 43 ( CTC )OCF0
93
2467L-AVR-05/04
Figure 43. T/C OCF0 fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
Figure 44 CTC OCF0 TCNT0 Figure 44. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
8 T/C
T/C TCCR0
Bit / 7 FOC0 W 0 6 WGM00 R/W 0 5 COM01 R/W 0 4 COM00 R/W 0 3 WGM01 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0
* Bit 7 - FOC0: FOC0 WGM PWM PWM TCCR0 1 OC0 COM01:0 FOC0 COM01:0
94
ATmega128
2467L-AVR-05/04
ATmega128
FOC0 OCR0 TOP CTC FOC0 0 * Bit 6, 3 - WGM01:0: TOP T/C (CTC) PWM Table 52 P 89" " Table 52.
0 1 2 3 Note: WGM01(1) (CTC0) 0 0 1 1 WGM00(1) (PWM0) 0 1 0 1 T/C PWM CTC PWM TOP 0xFF 0xFF OCR0 0xFF OCR0 TOP TOP TOV0 MAX BOTTOM MAX MAX
1. CTC0PWM0 WGM01:0
* Bit 5:4 - COM01:0: OC0 COM01:0 OC0 (DDR) OC0 OC0 COM01:0 WGM01:0 Table 53 WGM01:0 CTC COM01:0 Table 53. PWM
COM01 0 0 1 1 COM00 0 1 0 1 OC0 OC0 OC0 OC0
Table 54 WGM01:0 PWM COM01:0 Table 54. PWM (1)
COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0 OC0 TOP OC0 OC0 TOP OC0
1. OCR0 TOP COM01 TOP P 90" PWM "
Table 55 WGM01:0 PWM COM01:0
95
2467L-AVR-05/04
Table 55. PWM (1)
COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0 OC0 OC0 OC0 OC0
1. OCR0 TOP COM01 TOP P 92" PWM "
* Bit 2:0 - CS02:0: T/C Table 56 Table 56.
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C
clkT0S/( ) clkT0S/8 ( ) clkT0S/32 ( ) clkT0S/64 ( ) clkT0S/128 ( )
clkT0S/256 ( ) clkT0S/1024 ( )
T/C TCNT0
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0 TCNT0[7:0]
T/C 8 TCNT0 TCNT0 TCNT0 OCR0 OCR0
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0 R/W 0 OCR0[7:0]
8 TCNT0 OC0
96
ATmega128
2467L-AVR-05/04
ATmega128
/
ASSR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 AS0 R/W 0 2 TCN0UB R 0 1 OCR0UB R 0 0 TCR0UB R 0 ASSR
* Bit 3 - AS0: T/C0 AS0"0"T/C0I/OclkI/O AS0"1"T/CTOSC1 AS0 TCNT0 OCR0 TCCR0 * Bit 2 - TCN0UB: T/C0 T/C0 TCNT0TCN0UB TCNT0 TCN0UB TCN20UB 0 TCNT0 * Bit 1 - OCR0UB: 0 T/C0 OCR0OCR0UB OCR0 OCR0UB OCR0UB 0 OCR0 * Bit 0 - TCR0UB:T/C 0 T/C0 TCCR0TCR0UB TCCR0 TCR0UB TCR0UB 0 TCCR0 TCNT0OCR0 TCCR0 TCNT0 OCR0 TCCR0 T/C0 T/C0 * TCNT0 OCR0 TCCR0 1. OCIE0 TOIE0 T/C0 2. AS0 3. TCNT0 OCR0 TCCR0 4. TCN0UB OCR0UB TCR0UB 5. T/C0 6. * * 32.768 kHz TOSC1 T/C0 4 TCNT0 OCR0 TCCR0 TOSC1 3 TCNT0 OCR0 ASSR T/C0 MCU TCNT0 OCR0 TCCR0 Standby MCU T/C0 T/C0 MCU OCR0TCNT0 (OCR0UB0)MCU MCU T/C0Standby TOSC1
*
*
97
2467L-AVR-05/04
TOSC1 1. TCCR0 TCNT0 OCR0 2. ASSR 3. Standby * T/C0 32.768 kHz Standby 1 1 T/C0 T/C0 Standby 4 MCU SLEEP TCNT0 TCNT0 TOSC TCNT0 I/O TOSC1 I/O TCNT0 TOSC1 TOSC1 TCNT0 1. OCR0 TCCR0 2. 3. TCNT0 * 3
*
*
/ TIMSK
Bit /
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
* Bit 1 - OCIE0: T/C0 OCIE0 I '1' T/C0 T/C0 TIFR OCF0 * Bit 0 - TOIE0: T/C0 OCIE0 I '1' T/C0 T/C0 TIFR TOV0 / TIFR
Bit /
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 OCF0 R/W 0
0 TOV0 R/W 0 TIFR
* Bit 1 - OCF0: 0 T/C0 OCR0( 0) OCF0 1 SREG I OCIE0 OCF0 * Bit 0 - TOV0:T/C0 98
ATmega128
2467L-AVR-05/04
ATmega128
T/C0 TOV0 TOV0 1 SREG ITOIE0 TOV0 PWM T/C0 $00 TOV0
/
Figure 45. T/C0
clkI/O TOSC1 clkT0S Clear
10-BIT T/C PRESCALER
clkT0S/64
AS0
PSR0
0
CS00 CS01 CS02
TIMER/COUNTER0 CLOCK SOURCE clkT0
T/C0clkT0 T0 clkI/O clk ASSR AS0T/C0 TOSC1 T/C0 AS0 TOSC1 TOSC2 C ( 32.768 kHz ) TOSC1 T/C0 : clkT0S/8 clkT0S/32 clkT0S/64 clkT0S/128 clkT0S/256 clkT0S/1024 clkT0S 0 () SFIORPSR0 IO SFIOR
Bit / 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR0 R/W 0 0 PSR321 R/W 0 SFIOR
* Bit 7 - TSM:T/C TSM PSR0PSR321 TSM T/C TSM PSR T/C TSM T/C * Bit 1 - PSR0: T/C0 T/C0 T/C0 CPU T/C0
2467L-AVR-05/04
clkT0S/1024
clkT0S/32
clkT0S/128
clkT0S/256
clkT0S/8
99
16 / ( / 1 / 3)
16 T/C ( ) * 16 ( 16 PWM) * 3 * * * * ( ) * PWM * PWM * * * 10 (TOV1 OCF1AOCF1BOCF1CICF1 TOV3OCF3AOCF3B
OCF3C ICF3)
ATmega103
ATmega103 16 T/C(T/C1) ( A B) "n" T/C "x" 16 T/C Figure 46 P 2" " I/O CPU I/O I/O I/O I/O P 120"16 / "
100
ATmega128
2467L-AVR-05/04
ATmega128
Figure 46. 16 T/C
Count Clear Direction Control Logic TCLK TOVx (Int.Req.) Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Tx
Timer/Counter TCNTx
=
=0
OCFxA (Int.Req.)
=
OCRxA Fixed TOP Values
Waveform Generation
OCxA
OCFxB (Int.Req.) Waveform Generation OCxB
= DATABUS
OCRxB
OCFxC (Int.Req.)
=
OCRxC ICFx (Int.Req.) ICRx Edge Detector
Waveform Generation
OCxC
( From Analog Comparator Ouput )
Noise Canceler ICPx
TCCRxA
TCCRxB
TCCRxC
Note:
P 2Figure 1 P 69Table 30 P 75Table 39 T/C1 T/C3
/ TCNTn OCRnA/B/C ICRn 16 16 P 102" 16 " T/C TCCRnA/B/C 8 CPU ( Int.Req.)TIFRnETIFR TIMSKn ETIMSK (E)TIFRn (E)TIMSKn T/CTn T/C( ) T/C clkTn OCRnA/B/C T/C PWMOCnA/B/C P 108 "" OCFnA/B/C ICPn ( P 210 " " ) ( ) T/C ( )
101
2467L-AVR-05/04
TOP T/C OCRnA ICRn PWM OCRnA TOP OCRnA PWM OCRnA TOP TOP ICRn OCRnA PWM Table 57.
BOTTOM MAX TOP 0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCRnA ICRn
16T/C16AVRT/C * * * * * * * * * * * 16 T/C I/O 16 T/C PWMn0 WGMn0 PWMn1 WGMn1 CTCn WGMn2 T/C C (TCCRnC) C OCRnCH OCRnCL TCCR1A COM1C1:0 TCCRnC FOCnA FOCnB FOCnC TCCRnB WGMn3
16 T/C
16 T/C
C 16 T/C
16
TCNTn OCRnA/B/C ICRn AVR CPU 8 16 16 16 8 8 16 16 16 CPU 16 8 8 16 16 CPU 16 16 OCRnA/B/C 16 16
102
ATmega128
2467L-AVR-05/04
ATmega128
16 OCRnA/B/C ICRn "C" 16 (1)
... ; TCNTn 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; TCNTn r17:r16 in in ... r16,TCNTnL r17,TCNTnH
C (1)
unsigned int i; ... /* TCNTn 0x01FF */ TCNTn = 0x1FF; /* TCNTn i */ i = TCNTn; ...
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNTn r17:r16 16 16 16 16 16
103
2467L-AVR-05/04
TCNTn OCRnA/B/C ICRn (1)
TIM16_ReadTCNTn: ; in cli ; TCNTn r17:r16 in in r16,TCNTnL r17,TCNTnH r18,SREG ;
; out SREG,r18 ret
C (1)
unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNTn i */ i = TCNTn; /* */ SREG = sreg; return i; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNTn r17:r16
104
ATmega128
2467L-AVR-05/04
ATmega128
TCNTn OCRnA/B/C ICRn (1)
TIM16_WriteTCNTn: ; in cli ; TCNTn r17:r16 out TCNTnH,r17 out TCNTnL,r16 ; out SREG,r18 ret r18,SREG ;
C (1)
void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNTn i */ TCNTn = i; /* */ SREG = sreg; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
r17:r16 TCNTn 16
105
2467L-AVR-05/04
/
T/C T/C B(TCCRnB) (CSn2:0) P 130" / 3 / 2 / 1 " 16 T/C 16 Figure 47 Figure 47.
DATA BUS (8-bit)
TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn
( From Prescaler ) TOP BOTTOM
( ) Count Direction Clear clkTn TOP BOTTOM TCNTn 1 1 TCNTn / TCNTn TCNTn (0)
16 8 I/O TCNTnH 8 TCNTnL 8 CPU TCNTnH CPU TCNTnH (TEMP) TCNTnL TCNTnHTCNTnL TCNTnH CPU 8 16 TCNTn clkTn 1 1 clkTn CSn2:0 CSn2:0= 0 CPU TCNTn clkTn CPU TCCRnA TCCRnB WGMn3:0 ( ) OCnx P 111" " WGMn3:0 TOVn TOVn CPU
T/C ICPn
106
ATmega128
2467L-AVR-05/04
ATmega128
Figure 48 "n" / Figure 48.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int.Req.)
Note:
(ACO) T/C1 ICP - T/C3
ICPn ( ) ACO 16 TCNTn ICRn ICFn TICIEn = 1 ICFn I/O "1" ICRn ICRnL ICRnH TEMP CPU ICRnH TEMP ICRn ICRn TOP ICRn WGMn3:0 ICRn ICRnH I/O ICRnL P 102" 16 " 16 ICPnT/C1 ACSR ACIC ICPnACOTn(P 130Figure 59 ), 4 ICRn TOP T/C ICPn
107
2467L-AVR-05/04
4 4 TCCRnB ICNCn ICRn 4
ICRn ICRn ICRn TOP ICRn ICFn ( I/O "1") ICFn
16 TCNTn OCRnx OCFnx OCIEnx = 1 OCFnx OCFnx I/O "1" WGMn3:0 COMnx1:0 TOP BOTTOM (P 111 " " ) A T/C TOP ( ) TOP Figure 49 "n" (n = n T/Cn) "x" (A/B/C)
108
ATmega128
2467L-AVR-05/04
ATmega128
Figure 49.
DATABUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
T/C 12 PWM OCRnx (CTC) OCRnx TOP BOTTOM PWM OCRnx CPU OCRnx CPU OCRnx OCRnx( ) (T/C TCNT1 ICR1 ) OCR1x TEMP 16 OCR1x TEMP OCRnxH CPU I/O TEMP OCRnxL TEMP OCRnx OCRnx P 102" 16 " 16 PWM FOCnx "1" OCFnx / OCnx (COMx1:0 OCnx ) CPUTCNTn OCRnx TCNTn TCNTn TCNTn T/C TCNTnOCRnx PWM TOP
TCNTn
109
2467L-AVR-05/04
TCNTn TOP 0xFFFF TCNTnBOTTOM OCnx OCnx FOCnx OCnx COMnx1:0 COMnx1:0
110
ATmega128
2467L-AVR-05/04
ATmega128
COMnx1:0 COMnx1:0 OCnx COMnx1:0 OCnx Figure 50 COMnx1:0 I/O I/O I/O COMnx1:0 I/O (DDR PORT) OCnx OCnx OCnx COMnx "0" Figure 50.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COMnx1:0 OCnx I/O OCnx (DDR) OCnx DDR_OCnx Table 58 Table 59 Table 60 OCnx COMnx1:0 P 120 "16 / " COMnx1:0 COMnx1:0 CTC PWM COMnx1:0 = 0 OCnx PWMP 120Table 58 PWM P 121Table 59 PWM P 121Table 60 COMnx1:0 PWM FOCnx
- T/C - (WGMn3:0) (COMnx1:0) COMnx1:0 PWM PWM COMnx1:0 (P 111 " " ) P 117" / "
111
2467L-AVR-05/04
(WGMn3:0 = 0) (MAX = 0xFFFF) 0x0000 TCNTnT/CTOVn TOVn17 TOVn CPU
CTC( )
CTC (WGMn3:0 = 4 12) OCRnA ICRn TCNTn OCRnA(WGMn3:0 = 4) ICRn (WGMn3:0 = 12) OCRnA ICRn TOP CTCFigure 51 TCNTnTCNTnOCRnA ICRn TCNTn Figure 51. CTC
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
OCFnA ICFn TOP TOP CTC TOP BOTTOM OCRnA ICRn TCNTn 0xFFFF 0x0000 OCRnA ICRn PWM OCRnA TOP (WGMn3:0 = 15) OCRnA CTC OCnA COMnA1:0 = 1 OCnA (DDR_OCnA = 1) fOC0 = fclk_I/O/2 (OCRnA = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOVn MAX 0x0000
112
ATmega128
2467L-AVR-05/04
ATmega128
PWM PWM (WGMn3:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM TOP BOTTOM OCnx TCNTn OCRnx TOP OCRnx PWM PWM PWM DAC ( ) PWM PWM 89 10 ICRn OCRnA 2 (ICRn OCRnA 0x0003) 16 (ICRn OCRnA MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGMn3:0 = 5 6 7)ICRn (WGMn3:0 = 14) OCRnA (WGMn3:0 = 15) Figure 52 OCRnA ICRn TOP PWM TCNTn PWM PWM TCNTn OCRnx TCNTn OCnx Figure 52. PWM
OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
TOP T/C TOVn TOP OCRnA ICRn OCnA ICFn TOVn TOP TOPTOP TCNTnOCRnx TOP OCRnx "0" TOP ICRn OCRnA ICRn ICRn ICRn TCNTn 0xFFFF 0x0000 OCRnA OCRnA OCRnA TCNTn TOP OCRnA TCNTn TOVn 113
2467L-AVR-05/04
TOP ICRn TOP OCRnA OCnA PWM PWM ( TOP ) OCRnA PWM OCnx PWM COMnx1:0 2 PWM 3 PWM ( P 121Table 59 ) OCnx DDR_OCnx PWM OCnx OCRnx TCNTn ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP )
N (1 8 64 256 1024) OCRnx PWM OCRnx BOTTOM(0x0000) TOP+1OCRnxTOP COMnx1:0 OCnA (COMnA1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCRnA 0(0x0000) foc0 = fclk_I/O/2 CTC OCnA PWM PWM PWM (WGMn3:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNTn OCRnx OCnx BOTTOM TCNTn OCRnx OCnx PWM PWM 8 9 10 ICRn OCRnA 2 (ICRn OCRnA 0x0003) 16 (ICRn OCRnA MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGMn3:0 = 12 3) ICRn (WGMn3:0 = 10) OCRnA (WGMn3:0 = 11) TCNTn TOP Figure 53 OCRnA ICRn TOP PWM TCNTn PWM PWM TCNTn OCRnx TCNTn OCnx
114
ATmega128
2467L-AVR-05/04
ATmega128
Figure 53. PWM
OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
BOTTOM T/C TOVn TOP OCRnA ICRn OCRnx OCnA ICFn TOPTOP TCNTnOCRnx TOP OCRnx "0" Figure 53 T/C TOP OCRnx OCRnx / TOP PWM TOP TOP T/C TOP TOP PWM OCnx PWM COMnx1:0 2 PWM COMnx1:0 3 PWM ( P 121Table 60 ) OCnxDDR_OCnx OCRnx TCNTn OCnx PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCRnx PWM PWM OCRnx BOTTOM OCRnx TOP PWM OCnA TOP (WGMn3:0 = 11) COMnA1:0 = 1 OCnA 50% PWM PWM (WGMn3:0 = 8 9) - PWM - PWM PWM
115
2467L-AVR-05/04
BOTTOM TOP TOP BOTTOM TOP TCNTn OCRnx OCnxBOTTOMTCNTnOCRnx OCnx PWM PWM OCRnx Figure 53 Figure 54 PWM PWM ICRn OCRnA 2 (ICRn OCRnA 0x0003) 16 (ICRn OCRnA MAX) PWM
log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 )
PWM ICRn (WGMn3:0 = 8) OCRnA (WGMn3:0 = 9) TCNTn TOP Figure 54 OCRnA ICRn TOP PWM TCNTn PWM PWM TCNTn OCRnx TCNTn OCnx Figure 54. PWM
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
OCRnx T/C TOVn TOP OCRnA ICRn TCNTn TOP OCnA ICFn TOP BOTTOM TOPTOP TCNTnOCRnx 116
ATmega128
2467L-AVR-05/04
ATmega128
Figure 54 PWM OCRnx BOTTOM TOP ICRn TOP OCRnA OCnA PWM PWM ( TOP ) OCRnA PWM OCnx PWM COMnx1:0 2 PWM 3 PWM ( P 121Table 60 ) OCnx PWM OCnx OCRnx TCNTn ( ) TCNTn ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCRnx PWM PWM OCRnx BOTTOM OCRnx TOP PWM OCnA TOP (WGMn3:0 = 9) COMnA1:0 = 1 OCnA 50%
/
/ clkTn OCRnx OCRnx ( ) Figure 55 OCFnx Figure 55. T/C OCFnx
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 56
117
2467L-AVR-05/04
Figure 56. T/C OCFnx fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 57 TOP PWM OCRnx BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOVn Figure 57. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 58
118
ATmega128
2467L-AVR-05/04
ATmega128
Figure 58. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
119
2467L-AVR-05/04
16 /
/ 1 A TCCR1A
Bit / 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
COM1C1
2
COM1C0
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
/ 3 A TCCR3A
Bit /
7
COM3A1
6
COM3A0
5
COM3B1
4
COM3B0
3
COM3C1
2
COM3C0
1
WGM31
0
WGM30 TCCR3A
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7:6 - COMnA1:0: A * Bit 5:4 - COMnB1:0: B * Bit 3:2 - COMnC1:0: C COMnA1:0COMnB1:0 COMnC1:0 OCnA OCnB OCnC COMnA1:0 COMnB1:0COMnC1:0 "1" OCnA(OCnBOCnC) I/O OCnA(OCnB OCnC) OCnA(OCnB OCnC) COMnx1:0 WGMn3:0 Table 58 WGMn3:0 CTC ( PWM) COMnx1:0 Table 58. PWM
COMnA1/COMnB1/ COMnC1 0 0 1 1 COMnA0/COMnB0/ COMnC0 0 1 0 1 OCnA/OCnB/OCnC OCnA/OCnB/OCnC OCnA/OCnB/OCnC( ) OCnA/OCnB/OCnC( )
120
ATmega128
2467L-AVR-05/04
ATmega128
Table 59 WGMn3:0 PWM COMnx1:0 Table 59. PWM
COMnA1/COMnB1/ COMnC0 0 0 COMnA0/COMnB0/ COMnC0 0 1 OCnA/OCnB/OCnC WGMn3=0: OCnA/OCnB/OCnC WGMn3=1: OCnA OCnB/OCnC OCnA/OCnB/OCnC TOP OCnA/OCnB/OCnC OCnA/OCnB/OCnC TOP OCnA/OCnB/OCnC
1 1 Note:
0 1
OCRnA/OCRnB/OCRnCTOPCOMnA1/COMnB1/COMnC1 OCnA/OCnB/OCnC / P 113 " PWM "
Table 59WGMn3:0PWMPWMCOMnx1:0 Table 60. PWM
COMnA1/COMnB/ COMnC1 0 0 COMnA0/COMnB0/ COMnC0 0 1 OCnA/OCnB/OCnC WGMn3=0: OCnA/OCnB/OCnC WGMn3=1: OCnA OCnB/OCnC OCnA/OCnB/OCnC OCnA/OCnB/OCnC OCnA/OCnB/OCnC OCnA/OCnB/OCnC
1
0
1
1
Note:
OCRnA/OCRnB/OCRnCTOPCOMnA1/COMnB1/COMnC1 P 114 " PWM "
121
2467L-AVR-05/04
* Bit 1:0 - WGMn1:0: TCCRnB WGMn3:2 ---- ( Table 61)T/C ( ) (CTC) (PWM) (P 111 " " )
Table 61.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGMn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGMn2 (CTCn) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGMn1 (PWMn1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGMn0 (PWMn0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 / (1) 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCRnA 0x00FF 0x01FF 0x03FF ICRn OCRnA ICRn OCRnA ICRn - ICRn OCRnA OCRnx TOP TOP TOP TOP TOP TOP BOTTOM BOTTOM TOP TOP - TOP TOP TOVn MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
1. CTCn PWMn1:0 WGMn2:0
122
ATmega128
2467L-AVR-05/04
ATmega128
/ 1 B TCCR1B
Bit /
7 ICNC1 R/W 0
6 ICES1 R/W 0
5 - R 0
4 WGM13 R/W 0
3 WGM12 R/W 0
2 CS12 R/W 0
1 CS11 R/W 0
0 CS10 R/W 0 TCCR1B
/ 3 B TCCR3B
Bit /
7 ICNC3 R/W 0
6 ICES3 R/W 0
5 - R 0
4 WGM33 R/W 0
3 WGM32 R/W 0
2 CS32 R/W 0
1 CS31 R/W 0
0 CS30 R/W 0 TCCR3B
* Bit 7 - ICNCn: ICNC1 ICPn ICPn 4 4 4 * Bit 6 - ICESn: ICPn ICESn "0" ICESn "1" ICESn ICRn ICFn ICRn TOP ( TCCRnA TCCRnB WGMn3:0 ) ICPn * Bit 5 - TCCRnB "0" * Bit 4:3 - WGMn3:2: TCCRnA * Bit 2:0 - CSn2:0: 3 T/C Figure 55 Figure 56
123
2467L-AVR-05/04
Table 62.
CSn2 0 0 0 0 1 1 1 1 CSn1 0 0 1 1 0 0 1 1 CSn0 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) Tn Tn
Tn n T/Cn / 1 C TCCR1C
Bit /
7 FOC1A W 0
6 FOC1B W 0
5 FOC1C W 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 - R 0 TCCR1C
/ 3 C TCCR3C
Bit /
7 FOC3A W 0
6 FOC3B W 0
5 FOC3C W 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 - R 0 TCCR3C
* Bit 7 - FOCnA: A * Bit 6 - FOCnB: B * Bit 5 - FOCnC: C FOCnA/FOCnB/FOCnC WGMn3:0 PWM FOCnA/FOCnB/FOCnC "1" COMnx1:0 OCnA/OCnB/OCnC FOCnA/FOCnB/FOCnC COMnx1:0 FOCnA/FOCnB/FOCnC OCRnA TOP CTC FOCnA/FOCnB/FOCnC * Bit 4:0 - TCCRnC "0"
124
ATmega128
2467L-AVR-05/04
ATmega128
/ 1 TCNT1H TCNT1L
Bit
7
6
5
4
3
2
1
0 TCNT1H TCNT1L
TCNT1[15:8] TCNT1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
/ 3 TCNT3H TCNT3L
Bit
7
6
5
4
3
2
1
0 TCNT3H TCNT3L
TCNT3[15:8] TCNT3[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNTnHTCNTnLT/CnTCNTn / 16 CPU 8 TEMP TEMP 16 P 102 " 16 " TCNTnTCNTnOCRnx TCNTn 1 A OCR1AH OCR1AL
Bit
7
6
5
4
3
2
1
0 OCR1AH OCR1AL
OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1 B OCR1BH OCR1BL
Bit
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1 C OCR1CH OCR1CL
Bit
7
6
5
4
3
2
1
0 OCR1CH OCR1CL
OCR1C[15:8] OCR1C[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
3 A OCR3AH OCR3AL
Bit
7
6
5
4
3
2
1
0 OCR3AH OCR3AL
OCR3A[15:8] OCR3A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
3 B OCR3BH OCR3BL
Bit
7
6
5
4
3
2
1
0
125
2467L-AVR-05/04
OCR3B[15:8] OCR3B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
OCR3BH OCR3BL
3 C OCR3CH OCR3CL
Bit
7
6
5
4
3
2
1
0 OCR3CH OCR3CL
OCR3C[15:8] OCR3C[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
16 TCNTn OCnx 16 CPU 8 TEMP TEMP 16 P 102 " 16 " 1 ICR1H ICR1L
Bit
7
6
5
4 ICR1[7:0]
3
2
1
0 ICR1H ICR1L
ICR1[15:8] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
3 ICR3H ICR3L
Bit
7
6
5
4 ICR3[7:0]
3
2
1
0 ICR3H ICR3L
ICR3[15:8] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
ICPn( T/C1 ) TCNTn ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P 102 " 16 " / TIMSK
Bit /
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
Note:
T/C T1
* Bit 5 - TICIE1: T/C1 "1" I "1" T/C1 TIFR1 ICF1 CPU T/C1 ( P 55 " " ) * Bit 4 - OCIE1A:T/C1 A
126
ATmega128
2467L-AVR-05/04
ATmega128
"1" I "1" T/C1 A TIFR1 OCF1A CPU T/C1 A ( P 55 " " ) * Bit 3 - OCIE1B:T/C1 B "1" I "1" T/C1 B TIFR1 OCF1B CPU T/C1 B ( P 55 " " ) * Bit 2 - TOIE1:T/C1 "1" I "1" T/C1 TIFR TOV1 CPU T/C1 ( P 55 " " ) / ETIMSK
Bit /
7 - R 0
6 - R 0
5 TICIE3 R/W 0
4 OCIE3A R/W 0
3 OCIE3B R/W 0
2 TOIE3 R/W 0
1 OCIE3C R/W 0
0 OCIE1C R/W 0 ETIMSK
Note:
ATmega103
* Bit 7:6 - ETIMSK "0" * Bit 5 - TICIE3:T/C3, "1" I "1" T/C3 ETIFR ICF3 CPU T/C3 ( P 55 " " ) * Bit 4 - OCIE3A:T/C3 A "1" I "1" T/C3 A ETIFR OCF3A CPU T/C3 A ( P 55 " " ) * Bit 3 - OCIE3B:T/C3 B "1" I "1" T/C3 B ETIFR OCF3B CPU T/C3 B ( P 55 " " ) * Bit 2 - TOIE3:T/C3 "1" I "1" T/C3 ETIFR TOV3 CPU T/C3 ( P 55 " " ) * Bit 1 - OCIE3C:T/C3 C "1" I "1" T/C3 C ETIFR OCF3C CPU T/C3 C ( P 55 " " ) * Bit 0 - OCIE1C:T/C1 C "1" I "1" T/C1 C ETIFR OCF1C CPU T/C1 C ( P 55 " " )
127
2467L-AVR-05/04
/ TIFR
Bit /
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 OCF0 R/W 0
0 TOV0 R/W 0 TIFR
Note:
T/C T1
* Bit 5 - ICF1:T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1" * Bit 4 - OCF1A:T/C1 A TCNT1 OCR1A "1" (FOC1A) OCF1A A OCF1A "1" * Bit 3 - OCF1B:T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * Bit 2 - TOV1:T/C1 T/C1 CTC T/C1 TOV1 TOV1 P 122Table 61 OCF1A "1" / ETIFR
Bit /
7 - R/W 0
6 - R/W 0
5 ICF3 R/W 0
4 OCF3A R/W 0
3 OCF3B R/W 0
2 TOV3 R/W 0
1 OCF3C R/W 0
0 OCF1C R/W 0 ETIFR
* Bit 7:6 - ETIFR "0" * Bit 5 - ICF3:T/C3 ICP3 ICF3 ICR3 TOP TOP ICF3 ICF3 "1" * Bit 4 - OCF3A:T/C3 A TCNT3 OCR3A "1" (FOC3A) OCF3A 3A OCF3A "1" * Bit 3 - OCF3B:T/C3 B 128
ATmega128
2467L-AVR-05/04
ATmega128
TCNT3 OCR3B "1" (FOC3B) OCF3B 3B OCF3B "1" * Bit 2 - TOV3:T/C3 T/C3 CTC T/C3 TOV3 TOV3 P 95Table 52 OCF3B "1" * Bit 1 - OCF3C:T/C3 C TCNT3 OCR3C "1" (FOC3C) OCF3C 3C OCF3C "1" * Bit 0 - OCF1C:T/C1 C TCNT1 OCR1C "1" (FOC1C) OCF1C 1 C OCF1C "1"
129
2467L-AVR-05/04
/ 3 / 2 / 1
T/C3T/C1 T/C2 T/C3 T/C1 T/C2
CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C2T/C3 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C
Tn T/C clkT1/clkT2 /clkT3 Tn ( ) Figure 59 Tn clkI/O CSn2:0 = 7 clkT1/clkT2/clkT3 CSn2:0 = 6 clkT0 Figure 59. Tn
Tn
DQ LE
DQ
D
Q
Tn_sync (To Clock Select Logic)
clk I/O
Synchronization Edge Detector
Tn 2.5 3.5 Tn T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5
130
ATmega128
2467L-AVR-05/04
ATmega128
Figure 60. T/C1 T/C2 T/C3
CK
Clear
CK/8
10-BIT T/C PRESCALER CK/256 CK/1024 T1 CK/64
PSR321
T3
0
T2
0
0
CS30 CS31 CS32
CS20 CS21 CS22
CS10 CS11 CS12
TIMER/COUNTER3 CLOCK SOURCE clkT3
TIMER/COUNTER2 CLOCK SOURCE clkT2
TIMER/COUNTER1 CLOCK SOURCE clkT1
Note:
(T3/T2/T1) Figure 59
IO SFIOR
Bit / 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR0 R/W 0 0 PSR321 R/W 0 SFIOR
* Bit 7 - TSM:T/C TSM PSR0 PSR321 / T/C / T/C TSM / * Bit 0 - PSR321: T/C3 T/C2 T/C1 T/C3 T/C2 T/C1 TSM T/C3 T/C2 T/C1 "0"
131
2467L-AVR-05/04
PWM 8 / 2
T/C2 8 / * * ( ) * , (PWM) * * * 10 * (TOV2 OCF2) Figure 618T/C P 2"" CPUI/O I/O I/O I/O P 142"8 / " Figure 61. 8 T/C
TCCRn
count clear direction Control Logic Clock Select Edge Detector BOTTOM TOP
TOVn (Int.Req.) clk Tn
Tn
DATA BUS
( From Prescaler ) Timer/Counter TCNTn
=0
= 0xFF
OCn (Int.Req.)
=
Waveform Generation
OCn
OCRn
/ TCNT2 OCR2 8 ( Int.Req.) TIFR TIMSK TIFR TIMSK T/CT2 T/C ( ) T/C clkT0 OCR2 T/C PWM OC2 P 134 " " OCF2
"n" / 2 (TCNT2T/C2)
132
ATmega128
2467L-AVR-05/04
ATmega128
Table 63 Table 63. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR2
/
T/C T/C TCCR2 CS22:0 P 130"/ 3 / 2 / 1 " 8T/CFigure 62 Figure 62.
DATA BUS
TOVn (Int.Req.)
Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn
( ) count direction clear clkTn top bottom TCNT2 1 1 TCNT2 ( ) T/C TCNT2 TCNT2 (0)
clkT2 clkT2 CS02:0 (CS02:0 = 0) clkT2 CPU TCNT2 CPU ( ) T/C (TCCR2) WGM01 WGM00 OC2 P 135" " T/CTOV2WGM21:0 TOV2CPU
133
2467L-AVR-05/04
8 TCNT2 OCR2 TCNT2 OCR2 OCF2 OCIE2 = 1 OCF2 "1" WGM21:0 COM21:0 max bottom (P 135 " " ) Figure 63 Figure 63.
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.) top bottom FOCn
Waveform Generator
OCn
WGMn1:0
COMn1:0
PWM OCR2 OCR2 top bottom PWM OCR2 CPU OCR2 CPU OCR2 PWM FOC2 "1" OCF2 / OC2 (COM21:0 OC2 ) CPU TCNT2 OCR2 TCNT2 TCNT2 TCNT2 T/C TCNT2 OCR2 TCNT2 BOTTOM OC2 OC2 FOC2 OC2
TCNT2
134
ATmega128
2467L-AVR-05/04
ATmega128
COM21:0 COM21:0
COM21:0 COM21:0 (OC2) COM21:0 OC2 Figure 64 COM21:0 I/O I/O I/O COM21:0 I/O (DDR PORT) OC2 OC2 OC2 Figure 64.
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM21:0 OC2 I/O OC2 (DDR) OC2 DDR_OC2 OC2 COM21:0 P 142 "8 / " COM21:0 CTC PWM COM21:0 = 0 OC2 PWM P 143Table 65 PWM P 143Table 66 PWM P 143Table 67 COM21:0 PWM FOC2
- T/C - (WGM21:0) (COM21:0) COM21:0 PWM PWM COM21:0 (P 135 " " ) P 140" / " Figure 68 Figure 69Figure 70 Figure 71
135
2467L-AVR-05/04
(WGM21:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT2 T/C TOV2 TOV2 9 TOV2 CPU
CTC( )
CTC (WGM21:0 = 2) OCR2 TCNT2 OCR2 OCR2 TOP CTCFigure 65 TCNT2TCNT2OCR2 TCNT0 Figure 65. CTC
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
OCF2 TOP TOP CTC TOP BOTTOM OCR2 TCNT2 0xFF 0x00 OCR2 CTC OC2 COM21:0 = 1 OC2 fOC0 = fclk_I/O/2 (OCR2= 0x00) f clk_I/O f OCn = -----------------------------------------------2 N ( 1 + OCRn ) N (1 8 64 256 1024) TOV2 MAX 0x00 PWM PWM (WGM21:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC2 TCNT2 OCR2 BOTTOM OC2 PWM PWM
136
ATmega128
2467L-AVR-05/04
ATmega128
PWM DAC ( ) PWM MAX Figure 66 TCNT2 PWM PWM TCNT2 OCR2 TCNT2 Figure 66. PWM
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
MAX T/C TOV2 PWM OC2 PWM COM21:0 2 PWM 3 PWM ( P 143Table 66 ) OC2 PWM OC2 OCR2 TCNT2 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnPWM = -----------------N 256 N (1 8 64 256 1024) OCR2 PWM OCR2 BOTTOM MAX+1 OCR2 MAX COM21:0 OC2 (COM21:0 = 1) 50% OCR2 0 foc0 = fclk_I/O/2 CTC OC2 PWM
137
2467L-AVR-05/04
PWM
PWM (WGM21:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT2 OCR2 OC2 BOTTOM TCNT2 OCR2 OC2 PWM PWM 8 MAX TCNT2 MAX Figure 67 TCNT2 PWM PWM TCNT2 OCR2 TCNT2 Figure 67. PWM
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV2 PWM OC2 PWM COM21:0 2PWM COM21:03PWM (P 143Table 67 ) OC2 OCR2 TCNT2 OC2 PWM PWM f clk_I/O f OCnPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR2 PWM PWM OCR2 BOTTOM OCR2 MAX PWM Figure 67 OCn BOTTOM
138
ATmega128
2467L-AVR-05/04
ATmega128
* Figure 67 OCR0A MAX OCR0A MAX OCn BOTTOM OCn MAX OCR0A OCn
*
139
2467L-AVR-05/04
/
T/C clkT2 Figure 68 T/C PWM MAX Figure 68. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 69 Figure 69. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 70 ( CTC )OCF2
140
ATmega128
2467L-AVR-05/04
ATmega128
Figure 70. T/C OCF2 fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
Figure 71 CTC OCF2 TCNT2 Figure 71. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
141
2467L-AVR-05/04
8 /
/ TCCR2
Bit / 7 FOC2 W 0 6 WGM20 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 WGM21 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2
* Bit 7 - FOC2: FOC2 WGM20 PWM PWM TCCR2 1 OC2 COM21:0 FOC2 COM21:0 FOC2 OCR2 TOP CTC FOC2 0 * Bit 6, 3 - WGM21:0: TOP T/C (CTC) PWM Table 64 P 135" " Table 64.
0 1 2 3 Note: WGM21 (CTC2) 0 0 1 1 WGM20 (PWM2) 0 1 0 1 T/C PWM CTC PWM TOP 0xFF 0xFF OCR2 0xFF OCR2 TOP TOP TOV2 MAX BOTTOM MAX MAX
CTC2PWM2 WGM21:0
* Bit 5:4 - COM21:0: OC2 COM21:0 OC2 1 OC2 COM21:0 WGM21:0 Table 65 WGM21:0 CTC COM21:0
142
ATmega128
2467L-AVR-05/04
ATmega128
Table 65. PWM
COM21 0 0 1 1 COM20 0 1 0 1 OC2 OC2 OC2 OC2
Table 66 WGM21:0 PWM COM21:0 Table 66. PWM (1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 OC2 OC2 TOP OC2 OC2 TOP OC2
1. OCR2 TOP COM21 TOP P 136" PWM "
Table 67 WGM21:0 PWM COM21:0 Table 67. PWM (1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 OC2 OC2 OC2 OC2 OC2
1. OCR2 TOP COM21 TOP P 138" PWM "
* Bit 2:0 - CS22:0: T/C Table 68.
CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 T/C
clkI/O/( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( )
T2 T2
143
2467L-AVR-05/04
T/C2 T2 / TCNT2
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT2 R/W 0 TCNT2[7:0]
T/C 8 TCNT2 TCNT2 TCNT2 OCR2 OCR2
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR2 R/W 0 OCR2[7:0]
8 TCNT2 OC2 / TIMSK
Bit /
7 OCIE2 R/W 0
6 TOIE2 R/W 0
5 TICIE1 R/W 0
4 OCIE1A R/W 0
3 OCIE1B R/W 0
2 TOIE1 R/W 0
1 OCIE0 R/W 0
0 TOIE0 R/W 0 TIMSK
* Bit 7 - OCIE2:T/C2 OCIE2 I "1" T/C2 T/C2 TIFR OCF2 * Bit 6 - TOIE2:T/C2 TOIE2 I "1" T/C2 T/C2 TIFR TOV2 / TIFR
Bit /
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 OCF0 R/W 0
0 TOV0 R/W 0 TIFR
* Bit 7 - OCF2: 2 T/C2 OCR2( 2) OCF2 1 SREG IOCIE2 OCF2 * Bit 6 - TOV2:T/C2 T/C2 TOV2 TOV2 1 SREG I TOIE2 TOV2 PWM T/C2 $00 TOV2
144
ATmega128
2467L-AVR-05/04
ATmega128
(OCM1C2)
(OCM) 16 T/C1 8 T/C2 T/C P 100"16 / ( / 1 / 3)" P 132" PWM 8 / 2" ATmega103 Figure 72.
Timer/Counter 1
OC1C Pin
Timer/Counter 2
OC2
OC1C / OC2 / PB7
Figure 72
1C 2 PB7 ( COMnx1:0 0) (OC1C OC2) PORTB7 OC1C OC2 Figure 73 T/C B 7 Figure 73.
COM21 COM20 COM1C1 COM1C0
Modulator Vcc
0
( From Waveform Generator )
D
Q
1
OC1C
( From Waveform Generator )
1 Pin 0 OC1C / OC2 / PB7
D
Q
OC2 D Q D Q
PORTB7 DATABUS
DDRB7
( AND OR) PORTB7 COMnx1:0 DDRB7 Figure 74 T/C1 PWM T/C2 (COMnx1:0 = 1) CTC
145
2467L-AVR-05/04
Figure 74.
clk I/O OC1C
(FPWM Mode)
OC2
(CTC Mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1) 1 2 3
(Period)
T/C2 T/C1 C PWM (OC1C) (OC2) Figure 74 PORTB7 0 PB7 2 3 PB7
146
ATmega128
2467L-AVR-05/04
ATmega128
SPI
SPI ATmega128 ATmega128 SPI * 3 * * LSB MSB * 7 * * * * (CK/2) Figure 75. SPI
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
SPI P 2Figure 1 P 69Table 30
SPI Figure 76 SS SCK MOSI MOSI MISO MISO SS SPI SPI SS SPI SPI 8 SPI SPIF SPCR SPI SPIE SPDR SS 147
2467L-AVR-05/04
SPI2X
SS SPI MISO SPI SPDR SPIF SPCR SPI SPIE SPDR Figure 76. SPI -
SHIFT ENABLE
SPI SPI SPI SPI SCK SPI fosc/4 SPI MOSI MISO SCK SS Table 69 P 66" " Table 69. SPI (1)
MOSI MISO SCK SS Note: SPI SPI
1. P 69" B " SPI
SPI DDR_SPIDD_MOSI DD_MISODD_SCK
148
ATmega128
2467L-AVR-05/04
ATmega128
MOSI PB5 DD_MOSI DDB5 DDR_SPI DDRB (1)
SPI_MasterInit: ; MOSI SCK ldi out ldi out ret SPI_MasterTransmit: ; (r16) out SPDR,r16 Wait_Transmit: ; sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; SPI fck/16
C (1)
void SPI_MasterInit(void) { /* MOSI SCK */ DDR_SPI = (1<Note:
1.
149
2467L-AVR-05/04
SPI (1)
SPI_SlaveInit: ; MISO ldi out ldi out ret SPI_SlaveReceive: ; sbis SPSR,SPIF rjmp SPI_SlaveReceive ; in ret r16,SPDR r17,(1<; SPI
C (1)
void SPI_SlaveInit(void) { /* MISO */ DDR_SPI = (1<Note:
1.
150
ATmega128
2467L-AVR-05/04
ATmega128
SS
SPI SS SS SPI MISO ( ) SS SPI SS/ SS SPI SPI MSTR SPCR SS SS I/O SPI SS SS SPI SS SPI SPI 1. SPCR MSTR '0' SPI MOSI SCK 2. SPSR SPIF SPI SPI SS MSTR '1' SPI SPI SPCR
Bit / 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* Bit 7 - SPIE: SPI SPSR SPIF SREG SPI * Bit 6 - SPE: SPI SPE SPI * Bit 5 - DORD: DORD LSB MSB * Bit 4 - MSTR: / MSTR MSTR '1' SS MSTR SPSR SPIF MSTR * Bit 3 - CPOL: CPOLSCK SCK Figure 77 Figure 78 Table 70. CPOL
CPOL 0 1
* Bit 2 - CPHA:
151
2467L-AVR-05/04
CPHA SCK SCK Figure 77 Figure 78 Table 71. CPHA
CPHA 0 1
* Bits 1, 0 - SPR1, SPR0: SPI 1 0 SCK SPR1 SPR0 SCK fosc Table 72. SCK
SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK
fosc /4 fosc /16 fosc /64 fosc /128 fosc /2 fosc /8 fosc /32 fosc /64
152
ATmega128
2467L-AVR-05/04
ATmega128
SPI SPSR
Bit / 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* Bit 7 - SPIF: SPI SPIF SPCR SPIE SPI SPI SS SPIF SPIF SPSR SPDR SPIF * Bit 6 - WCOL: SPI SPDR WCOL WCOL SPSR SPDR * Bit 5..1 - Res: * Bit 0 - SPI2X:SPI SPI SCK CPU fosc /4 ATmega128 SPI EEPROM SPI SPI SPDR
Bit / 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X SPDR
SPI / SPI
153
2467L-AVR-05/04
SCK 4 CPHA CPOL SPI Figure 77 Figure 78 SCK Table 70 Table 71 Table 73. CPOL CPHA
CPOL = 0, CPHA = 0 CPOL = 0, CPHA = 1 CPOL = 1, CPHA = 0 CPOL = 1, CPHA = 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) SPI 0 1 2 3
Figure 77. CPHA = 0 SPI
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 78. CPHA = 1 SPI
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
154
ATmega128
2467L-AVR-05/04
ATmega128
USART
(USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * ATmega128 USART USART0 USART1 USART USART0 USART1 I/O P 342" " ATmega103 USART1 UBRR0H UCRS0C ATmega103 ATmega128 USART0 Figure 79 USART CPU I/O I/O
USART
155
2467L-AVR-05/04
Figure 79. USART
Clock Generator
UBRR[H:L] OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCK
Transmitter
UDR (Transmit) PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxD TX CONTROL
DATABUS
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxD
UDR (Receive)
PARITY CHECKER
UCSRA
UCSRB
UCSRC
Note:
P 2Figure 1 , P 73Table 36 P 75Table 39 USART
USART XCK ( ) USART UDR
156
ATmega128
2467L-AVR-05/04
ATmega128
AVR USART AVR UART USART AVR UART * * * * * * USART FIFO FE DOR 9 RXB8 UDR ( Figure 79) USART (DOR) CHR9 UCSZ2 OR DOR
*
* *
USART 4 : USART C (UCSRC) ( ) UCSRA U2X (UMSEL = 1) XCK (DDR_XCK)()() XCK Figure 80 Figure 80.
UBRR fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 U2X
0 1 0 DDR_XCK 1
OSC
txclk
xcki XCK Pin xcko
Sync Register
Edge Detector
0 1
UMSEL
DDR_XCK
UCPOL
1 0
rxclk
txclk rxclk xcki xcko ( ) ( ) XCK ( ) XCK ( ). 157
2467L-AVR-05/04
fosc
XTAL ( )
Figure 80 USART UBRR UBRRL UBRR fosc/(UBRR+1) 2 8 16 2 816 UMSEL U2X DDR_XCK Table 74(/)UBRR Table 74.
(U2X = 0) (U2X = 1) (1) UBRR
f OSC BAUD = --------------------------------------16 ( UBRR + 1 ) f OSC BAUD = -----------------------------------8 ( UBRR + 1 ) f OSC BAUD = -----------------------------------2 ( UBRR + 1 )
f OSC UBRR = ----------------------- - 1 16BAUD f OSC UBRR = -------------------- - 1 8BAUD f OSC UBRR = -------------------- - 1 2BAUD
Note:
1. (bps)
BAUD ( bps) fOSC UBRR UBRRH UBRRL (0-4095) Table 82 UBRR (U2X) UCSRA U2X "0" 16 8 Figure 80 XCK CPU XCK f OSC f XCK < -----------4 fosc (UMSEL = 1)XCK ( ) ( ) TxD XCK RxD
158
ATmega128
2467L-AVR-05/04
ATmega128
Figure 81. XCK .
UCPOL = 1
XCK RxD / TxD Sample
UCPOL = 0
XCK RxD / TxD Sample
UCRSC UCPOL XCK Figure 81 UCPOL=0 XCK XCK UCPOL=1 XCK XCK
159
2467L-AVR-05/04
( ) USART 30 * * * * 1 5 6 7 8 9 1 2
9 Figure 82 Figure 82.
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St (n) P Sp IDLE
(0 8) (RxD TxD)
UCSRB UCSRC UCSZ2:0 UPM1:0 USBS USART UCSZ2:0 UPM1:0 USBS (FE) "0" P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n
USART
USART USART ( ) USART TXC RXC ( UDR )TXC
160
ATmega128
2467L-AVR-05/04
ATmega128
USART ( ) r17:r16 (1)
USART_Init: ; out out ldi out ldi out ret UBRRH, r17 UBRRL, r16 r16, (1<;
; : 8 , 2
C (1)
void USART_Init( unsigned int baud ) { /* */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* */ UCSRB = (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O
USART UCSRB TXEN USART TxD
I/O USART XCK CPU UDR ( )
5 8
161
2467L-AVR-05/04
UDRE 8 UDR USART R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; out ret UDR,r16
C (1)
void USART_Transmit( unsigned char data ) { /* */ while ( !( UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
UDRE
162
ATmega128
2467L-AVR-05/04
ATmega128
9 9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 R17:R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRB,TXB8 UCSRB,TXB8 UDR,r16 sbrc r17,0 ; 8
C
void USART_Transmit( unsigned int data ) { /* */ while ( !( UCSRA & (1<Note:
1. UCSRB UCSRB TXB8 I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
9 USART USART UDRE TXC UDRE "1" UCSRA "0" UCSRB UDRIE "1" UDRE ( ) USART UDR UDRE UDR UDRE TXC TXC "1" TXC
163
2467L-AVR-05/04
RS-485 UCSRB TXCIE "1" TXC USART TXC TXC (UPM1 = 1) TXEN TxD I/O
USART UCSRB (RXEN) USART RxD
USART XCK
5 8
XCK UDR
164
ATmega128
2467L-AVR-05/04
ATmega128
RXC 8 UDR 0 USART (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; in ret r16, UDR
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !(UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
RXC
165
2467L-AVR-05/04
9
9 (UCSZ=7) UDR 8 UCSRB RXB8 9 FE DOR UPE UCSRA UDR UDR FIFO FIFO TXB8 FE DOR UPE USART 9 (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; 9 in in in r18, UCSRA r17, UCSRB r16, UDR
; -1 andi r18,(1<USART_ReceiveNoError: ; 9 lsr ret r17 andi r17, 0x01
C (1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O 166
ATmega128
2467L-AVR-05/04
ATmega128
USART (RXC) 1 0( ) (RXEN = 0) RXC UCSRB (RXCIE) RXC ( ) USART UDR RXC USART (FE) (DOR) (UPE) UCSRA UDR UCSRA (UDR) "0" (FE) ( 1) FE 0 FE 1 UCSRC USBS FE UCSRA 0 (DOR) ( ) DOR UDR UDR UCSRA 0 DOR (UPE) UPE UCSRA 0 P 160" " P 168" "
167
2467L-AVR-05/04
UPM1 ( ) UPM0 (UPE) (UPM1 = 1) UPE (UDR)
(RXEN ) RxD FIFO FIFO UDR RXC (1)
USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush
C (1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
USART RxD
168
ATmega128
2467L-AVR-05/04
ATmega128
Figure 83 16 8 (U2X = 1) RxD ( ) 0 Figure 83.
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
RxD ( ) ( ) 1 0 8 9 10( ) 4 5 6( ) ( ) 16 8 Figure 84 Figure 84.
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
2 3 1 2 3 0RxD Figure 85
169
2467L-AVR-05/04
Figure 85.
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
0 FE Figure 85 A B C ( Table 75)
( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF D S SF SM (D = 5 10 )
( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M
S = 16 S = 8 SF = 8 SF = 4 SM = 9 SM = 5
Rslow Rfast Table 75 Table 76 Table 75. (U2X = 0)
D # ( + ) 5 6 7 8 9 10 Rslow % 93,20 94,12 94,81 95,36 95,81 96,17 Rfast % 106,67 105,79 105,11 104,58 104,14 103,78 % (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.5 2.0 2.0 1.5 1.5
170
ATmega128
2467L-AVR-05/04
ATmega128
Table 76. (U2X = 1)
D # + 5 6 7 8 9 10 Rslow (%) 94,12 94,92 95,52 96,00 96,39 96,70 Rfast (%) 105,66 104,92 104,35 103,90 103,53 103,23 (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0
(XTAL) 2% UBRR
UCSRA (MPCM) USART CPU MPCM 5 8 9 9 (RXB8) ( 9 ) 1
MPCM
9 (UCSZ = 7) (TXB8 = 1) 9 (TXB8) 1 (TXB = 0) 9 1. (UCSRA MPCM ) 2. UCSRA RXC 3. UDR UCSRA MPCM MPCM 1 4. MPCM 1 5. MPCM 2
171
2467L-AVR-05/04
5 8 n n+1 5 8 (USBS = 1) - - (SBI CBI) MPCM MPCM TXC I/O SBI CBI
172
ATmega128
2467L-AVR-05/04
ATmega128
USART
USARTn I/O UDRn
Bit 7 6 5 4 3 2 1 0 UDRn ( ) UDRn ( ) R/W 0 R/W 0 R/W 0
RXBn[7:0] TXBn[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
USART USART I/O USART UDR UDR (TXB) UDR (RXB) 567 0 UCSRA UDRE UDRE UDR USART TxD FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO USART A UCSRnA
Bit /
7 RXCn R 0
6 TXCn R/W 0
5 UDREn R 1
4 FEn R 0
3 DORn R 0
2 UPEn R 0
1 U2Xn R/W 0
0 MPCMn R/W 0 UCSRnA
* Bit 7 - RXCn: USART RXCn RXCn RXCn ( RXCIEn ) * Bit 6 - TXCn: USART (UDRn) TXCn TXCn 1 TXCn ( TXCIEn ) * Bit 5 - UDREn: USART UDREn (UDRn) UDREn 1 UDREn ( UDRIEn ) UDREn * Bit 4 - FEn: 0 FEn (UDRn) 1 FEn 0 UCSRnA 0 * Bit 3 - DORn: DORn ( ) (UDRn) UCSRnA 0 * Bit 2 - UPEn:
173
2467L-AVR-05/04
(UPMn1 = 1) UPEn (UDRn) UCSRnA 0 * Bit 1 - U2Xn: 1 16 8 * Bit 0 - MPCMn: MPCMn USARTn MPCMn P 171" " USARTn B UCSRnB
Bit /
7 RXCIEn R/W 0
6 TXCIEn R/W 0
5 UDRIEn R/W 0
4 RXENn R/W 0
3 TXENn R/W 0
2 UCSZn2 R/W 0
1 RXB8n R 0
0 TXB8n R/W 0 UCSRnB
* Bit 7 - RXCIEn: RXCn RXCIEn 1 SREG UCSRnA RXCn 1 USARTn * Bit 6 - TXCIE: TXCn TXCIEn 1 SREG UCSRnA TXCn 1 USARTn * Bit 5 - UDRIEn: USART UDREn UDRIEn 1 SREG UCSRnA UDREn 1 USARTn * Bit 4 - RXENn: USARTn RxDn USARTn FEn DORn UPEn * Bit 3 - TXENn: USARTn TxDn USARTn TXENn TxDn I/O * Bit 2 - UCSZn2: UCSZn2 UCSRnC UCSZn1:0 ( ) * Bit 1 - RXB8n: 8 9 RXB8n 9 UDRn RXB8n * Bit 0 - TXB8n: 8 9 TXB8n9 UDRn USART C UCSRnC
Bit
7
-
6
UMSELn
5
UPMn1
4
UPMn0
3
USBSn
2
UCSZn1
1
UCSZn0
0
UCPOLn UCSRnC
174
ATmega128
2467L-AVR-05/04
ATmega128
/ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 0
ATmega103 * Bit 7 - UCSRnC 0 * Bit 6 - UMSELn: USART Table 77. UMSELn
UMSELn 0 1
* Bit 5:4 - UPMn1:0: UPMn0 UCSRnA UPEn Table 78. UPMn
UPMn1 0 0 1 1 UPMn0 0 1 0 1
* Bit 3 - USBSn: Table 79. USBSn
USBSn 0 1 1-bit 2-bits
* Bit 2:1 - UCSZn1:0: UCSZn1:0 UCSRnB UCSZn2( ) Table 80. UCSZn
UCSZn2 0 0 0 0 UCSZn1 0 0 1 1 UCSZn0 0 1 0 1 5 6 7 8
175
2467L-AVR-05/04
Table 80. UCSZn
UCSZn2 1 1 1 1 UCSZn1 0 0 1 1 UCSZn0 0 1 0 1 9
* Bit 0 - UCPOLn: UCPOLn XCKn Table 81. UCPOLn
UCPOLn 0 1 (TxDn ) XCKn XCKn (RxDn ) XCKn XCKn
USART UBRRnL UBRRnH
Bit
15 - 7
14 - 6 R R/W 0 0
13 - 5 R R/W 0 0
12 -
11
10
9
8 UBRRnH UBRRnL 0 R/W R/W 0 0
UBRRn[11:8] 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0
UBRRn[7:0] 4 R R/W 0 0 / R R/W 0 0
UBRRnH mega103 * Bit 15:12 - UBRRnH * Bit 11:0 - UBRRn11:0: USARTn 12 USARTn UBRRnH USARTn 4 UBRRnL 8 UBRRnL
176
ATmega128
2467L-AVR-05/04
ATmega128
Table 82 UBRR 0.5% ( P 170" " )
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
Table 82. UBRR
fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 1.
(1)
fosc = 1.8432 MHz U2X = 0 UBRR 47 23 11 7 5 3 2 1 1 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRR 95 47 23 15 11 7 5 3 2 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% - 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - UBRR 51 25 12 8 6 3 2 1 1 0 - -
fosc = 2.0000 MHz U2X = 0 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - 125 kbps U2X = 1 UBRR 103 51 25 16 12 8 6 3 2 1 - 0 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0% 250 kbps
U2X = 0 UBRR 25 12 6 3 2 1 1 0 - - - - 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - -
U2X = 1 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps
62.5 kbps UBRR = 0, = 0.0%
115.2 kbps
230.4 kbps
177
2467L-AVR-05/04
Table 83. UBRR
fosc = 3.6864 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 4.0000 MHz U2X = 0 UBRR 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
fosc = 7.3728 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
U2X = 0 UBRR 95 47 23 15 11 7 5 3 2 1 0 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
U2X = 1 UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
230.4 kbps UBRR = 0, = 0.0%
460.8 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
178
ATmega128
2467L-AVR-05/04
ATmega128
Table 84. UBRR
fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 11.0592 MHz U2X = 0 UBRR 287 143 71 47 35 23 17 11 8 5 2 2 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 575 287 143 95 71 47 35 23 17 11 5 5 2 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0
fosc = 14.7456 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRR 767 383 191 127 95 63 47 31 23 15 7 6 3 1 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
U2X = 0 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
U2X = 1 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0
0.5 Mbps UBRR = 0, = 0.0%
1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
179
2467L-AVR-05/04
Table 85. UBRR
fosc = 16.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 18.4320 MHz U2X = 0 UBRR 479 239 119 79 59 39 29 19 14 9 4 4 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 959 479 239 159 119 79 59 39 29 19 9 8 4 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% - 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0% UBRR 520 259 129 86 64 42 32 21 15 10 4 4 - -
fosc = 20.0000 MHz U2X = 0 0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - - U2X = 1 UBRR 1041 520 259 173 129 86 64 42 32 21 10 9 4 - 0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% -
U2X = 0 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps UBRR = 0, = 0.0%
U2X = 1 UBRR 832 416 207 138 103 68 51 34 25 16 8 7 3 1
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
180
ATmega128
2467L-AVR-05/04
ATmega128
TWI
* * * * * * * * * *
7 128 400 kHz AVR
TWI TWI 128 SCL SDA TWI Figure 86. TWI
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
TWI
Table 86. TWI
SCL
Figure 86 TWI TWI "0" TWI TWI TWI AVR 400 pF 7 TWI P 302" " 100 kHz 400 kHz
181
2467L-AVR-05/04
( ) TWI Figure 87.
SDA
SCL Data Stable Data Stable
Data Change
START/STOP
START STOP START STOP START STOP START REPEATED START REPEATED START STOP START START REPEATED START START START STOP SCL SDA Figure 88. START REPEATED START STOP
SDA
SCL
START
STOP START
REPEATED START
STOP
TWI 9 7 1 READ/WRITE 1 READ/WRITE 1 SCL (ACK) SDA ACK SDA STOP REPEATED START SLA+R SLA+W READ WRITE MSB 0000 000 ACK SDA Write ACK SDA Read 1111 xxx
182
ATmega128
2467L-AVR-05/04
ATmega128
Figure 89.
Addr MSB SDA Addr LSB R/W ACK
SCL 1 START 2 7 8 9
TWI 9 8 1 START STOP 9 SCL SDA SDA NACK NACK MSB Figure 90.
Data MSB Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 SLA+R/W 2 7 Data Byte 8 9 STOP, REPEATED START or Next Data Byte Data LSB ACK

START SLA+R/W STOP START STOP SCL SCL SCL SCL SCL SCL SCL TWI Figure 91 SLA+R/W STOP Figure 91.
Addr MSB SDA Addr LSB R/W ACK Data MSB Data LSB ACK
SCL 1 START 2 7 SLA+R/W 8 9 1 2 Data Byte 7 8 9 STOP
183
2467L-AVR-05/04
TWI
*
*
SCL
SCL / SCL / Figure 92. SCL
TA low TA high
SCL from master A
SCL from master B
SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period
SDA SDA SDA SDA
184
ATmega128
2467L-AVR-05/04
ATmega128
Figure 93. START
SDA from Master A
Master A loses Arbitration, SDAA SDA
SDA from Master B
SDA Line
Synchronized SCL Line
* * * REPEATED START STOP REPEATED START STOP
SLA+R/W
185
2467L-AVR-05/04
TWI
TWI Figure 94 AVR Figure 94. TWI
SCL
Slew-rate Control Spike Filter
SDA
Slew-rate Control Spike Filter
Bus Interface Unit
START / STOP Control Spike Suppression
Bit Rate Generator
Prescaler
Arbitration detection
Address/Data Shift Register (TWDR)
Ack
Bit Rate Register (TWBR)
Address Register (TWAR)
Status Register (TWSR)
Control Register (TWCR)
Address Comparator
State Machine and Status control
Scl SDA
SCL SDAMCU TWI TWI 50 ns SCL SDA I/O TWI SCL TWI TWSR TWBR TWI CPU TWI SCL 16 SCL TWI SCL CPU Clock frequency SCL frequency = -----------------------------------------------------------TWPS 16 + 2(TWBR) 4 * * TWBR = TWI TWPS = TWI
TWI TWBR 10 SDA SCL TWI Start + SLA + R/W ( )
Note:
TWDRSTART/STOP TWDR 8 TWDR (N)ACK (N)ACK TWI TWCR (N)ACK TWCR START/STOP TWI START REPEATED START STOP MCU START/STOP TWI
186
ATmega128
2467L-AVR-05/04
TWI Unit
Address Match Unit
Control Unit
ATmega128
START/STOP TWI MCU TWI TWI TWAR 7 TWAR TWI TWGCE "1" TWI TWCR MCU MCU TWI MCU TWI TWI TWI TWI TWCR TWI TWI TWINT TWI TWSR TWSR TWINT "1" SCL TWI TWINT * * * * * * * * TWI START/REPEATED START TWI SLA+R/W TWI TWI TWI ( ) TWI TWI STOP REPEATED START START STOP
187
2467L-AVR-05/04
TWI
TWI TWBR
Bit / 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR
* Bits 7..0 - TWI TWBR SCL P 186" " TWI TWCR
Bit / 7 TWINT R/W 0 6 TWEA R/W 0 5 TWSTA R/W 0 4 TWSTO R/W 0 3 TWWC R 0 2 TWEN R/W 0 1 - R 0 0 TWIE R/W 0 TWCR
TWCR TWI TWI START STOP TWDR TWDR TWDR * Bit 7 - TWINT: TWI TWI TWINT SREG I TWCR TWIE MCU TWI TWINT SCL TWINT "1" "0" TWI TWINT TWAR TWSR TWDR * Bit 6 - TWEA: TWI TWEA TWEA ACK 1. 2. TWAR TWGCE 3. / TWEA * Bit 5 - TWSTA: TWI START CPU TWSTA TWI START STOP START START TWSTA * Bit 4 - TWSTO: TWI STOP TWSTOTWI STOP TWSTO TWSTO STOP TWI SCL SDA * Bit 3 - TWWC: TWI TWINT TWDR TWWC TWDR
188
ATmega128
2467L-AVR-05/04
ATmega128
* Bit 2 - TWEN: TWI TWEN TWITWI TWEN"1" TWII/O SCL SDA TWI TWI * Bit 1 - Res: "0" * Bit 0 - TWIE: TWI SREG I TWIE TWINT "1" TWI TWI TWSR
Bit / 7 TWS7 R 1 6 TWS6 R 1 5 TWS5 R 1 4 TWS4 R 1 3 TWS3 R 1 2 - R 0 1 TWPS1 R/W 0 0 TWPS0 R/W 0 TWSR
* Bits 7..3 - TWS: TWI 5 TWI TWSR 5 2 "0" * Bit 2 - Res: "0" * Bits 1..0 - TWPS: TWI / Table 87. TWI
TWPS1 0 0 1 1 TWPS0 0 1 0 1 1 4 16 64
P 186" " TWPS1..0 TWI TWDR
Bit / 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR
TWDR TWDR TWI (TWINT ) TWINT TWDR TWDR MCU TWI TWDR ACK TWI CPU ACK * Bits 7..0 - TWD: TWI
189
2467L-AVR-05/04
TWI( ) TWAR
Bit /
7 TWA6 R/W 1
6 TWA5 R/W 1
5 TWA4 R/W 1
4 TWA3 R/W 1
3 TWA2 R/W 1
2 TWA1 R/W 1
1 TWA0 R/W 1
0 TWGCE R/W 0 TWAR
TWAR 7 TWI TWAR TWAR LSB (0x00) * Bits 7..1 - TWA: TWI * Bit 0 - TWGCE: TWI MCU TWI
TWI
AVR TWI START TWI TWI TWI TWCR TWI TWIESREGTWINT TWIE TWINT TWI TWINT "1" TWI TWI TWSR TWI TWCR TWCR TWDR TWI TWI Figure 95 TWI
190
ATmega128
2467L-AVR-05/04
ATmega128
Figure 95. TWI
Application Action
1. Application writes to TWCR to initiate transmission of START 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero. 5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one. 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one
TWI bus
START
SLA+W
A
Data
A
STOP
TWI Hardware Action
2. TWINT set. Status code indicates START condition sent
4. TWINT set. Status code indicates SLA+W sendt, ACK received
6. TWINT set. Status code indicates data sent, ACK received
Indicates TWINT set
1. TWI START TWCR TWI START TWINT TWINT "1" TWCR TWINT TWI TWINT TWI START 2. START TWCR TWINTTWCR START 3. TWSR START TWSR SLA+W TWDR TWDR TWDR SLA+W TWCR TWI SLA+W TWINT TWINT "1" TWCR TWINT TWI TWINT TWI 4. TWCR TWINT TWDR 5. TWSRACK TWSR TWDR TWCR TWI TWDR TWINT TWCR TWINT TWI TWINT TWI 6. TWCR TWINT TWSR 7. TWSR ACK TWSR TWCR TWI STOP TWINT TWINT "1" TWCR TWINT TWI TWINT TWI STOP TWINT STOP
191
2467L-AVR-05/04
TWI * * * TWI TWINT TWINT SCL TWINT TWI TWI TWDR TWI TWCR TWCR TWINT TWINT "1" TWI TWCR
C
192
ATmega128
2467L-AVR-05/04
ATmega128
1 ldi r16, (1<C
TWCR = (1<while (!(TWCR & (1< TWINT TWINT START
if ((TWSR & 0xF8) != START) ERROR();
TWI START
TWDR = SLA_W; TWCR = (1< SLA_W TWDR TWINT
while (!(TWCR & (1< TWINT TWINT SLA+W ACK/NACK TWI MT_SLA_ACK TWDR TWINT
if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR();
TWDR = DATA; TWCR = (1<while (!(TWCR & (1< TWINT TWINT DATA ACK/NACK TWI MT_DATA_ACK
if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR();
TWCR = (1< I/O I/O "LDS" "STS" "SBRS" "SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
193
2467L-AVR-05/04
TWI 4 (MT) (MR) (ST) (SR) TWI MT TWI EEPROM MR EEPROM TWI SR S START RsREPEATED START R (SDA ) W (SDA ) A (SDA ) A (SDA ) Data8 P STOP SLA Figure 97 Figure 103 TWINT TWSR 0 / TWI TWI TWINT TWINT TWSR Table 88 Table 91 0
Figure 96 START MT MR SLA+W MT SLA+R MR "0" Figure 96.
VCC
Device 1
MASTER TRANSMITTER
Device 2
SLAVE RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
194
ATmega128
2467L-AVR-05/04
ATmega128
TWEN TWSTA"1"START TWINT "1" TWINT TWI START TWINT TWSR $08 ( Table 88) MT SLA+W TWDR SLA+W TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+W TWINT TWSR $18 $20 $38 Table 88 SLA+W TWDR TWDR TWINT TWCR TWWC TWDR TWINT TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
REPEATED START ( $10) STOP REPEATED START Table 88.
(TWSR) "0"
$08
TWCR 2 2 START START / TWDR SLA+W SLA+W SLA+R STA
0
STO
0
TWIN T
1
TWE A
X
2 SLA+W ACK NOT ACK SLA+W ACK NOT ACK SLA+R
$10
0 0
0 0
1 1
X X
$18
SLA+W ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO
195
2467L-AVR-05/04
Table 88.
$20
SLA+W NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO
$28
ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO
$30
NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
$38
SLA+W
TWDR TWDR
0 1
0 0
1 1
X X
2 START
196
ATmega128
2467L-AVR-05/04
ATmega128
Figure 97.
MT
Successfull transmission to a slave receiver
S
SLA
W
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$18
$28
RS
SLA
W
$10
Not acknowledge received after the slave address
A
P
R
$20
MR
Not acknowledge received after a data byte
A
P
$30
Arbitration lost in slave address or data byte
A or A
Other master continues
A or A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
197
2467L-AVR-05/04
Figure 98 START MT MR SLA+W MT SLA+R MR "0" Figure 98.
VCC
Device 1
MASTER RECEIVER
Device 2
SLAVE TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN TWSTA"1"START TWINT "1" TWINT TWI START TWINT TWSR $08 ( Table 88) MR SLA+R TWDR SLA+R TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+R TWINT TWSR $38 $40 $48 Table 97 TWDR TWINT MR NACK STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
REPEATED START ( $10) STOP REPEATED START
198
ATmega128
2467L-AVR-05/04
ATmega128
Figure 99.
MR
Successfull reception from a slave receiver
S
SLA
R
A
DATA
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$40
$50
$58
RS
SLA
R
$10
Not acknowledge received after the slave address
A
P
W
$48
MT
Arbitration lost in slave address or data byte
A or A
Other master continues
A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
199
2467L-AVR-05/04
Table 89.
(TWSR) "0"
$08
TWCR 2 2 START START / TWDR SLA+R SLA+R SLA+W STA
0
STO
0
TWIN T
1
TWE A
X
2 SLA+R ACK NOT ACK SLA+R ACK NOT ACK SLA+W
$10
0 0
0 0
1 1
X X
$38
SLA+R NOT ACK SLA+R ACK SLA+R NOT ACK
TWDR TWDR
0 1
0 0 0 0 0 1 1
1 1 1 1 1 1 1
X X 0 1
2 START NOT ACK ACK
$40
TWDR TWDR
0 0
$48
TWDR TWDR TWDR
1 0 1
X X X
START STOP TWSTO STOP START TWSTO
$50
ACK NOT ACK

0 0
0 0 0 1 1
1 1 1 1 1
0 1
NOT ACK ACK
$58

1 0 1
X X X
START STOP TWSTO STOP START TWSTO
Figure 100 "0" Figure 100.
VCC
Device 1
SLAVE RECEIVER
Device 2
MASTER TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
200
ATmega128
2467L-AVR-05/04
ATmega128
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
201
2467L-AVR-05/04
7 TWI LSB TWI $00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) 0 ( ) TWINT TWSR Table 90 TWI ( $68 $78) CPU TWEA TWI SDA " " TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVRTWI AVR SCL MCU TWDR
202
ATmega128
2467L-AVR-05/04
ATmega128
Table 90.
(TWSR) "0"
$60
TWCR 22 SLA+W ACK SLA+R/W SLA+W ACK ACK SLA+R/W ACK SLA+W ACK SLA+W NOT ACK / TWDR TWDR TWDR STA
X X
STO
0 0 0 0
TWIN T
1 1 1 1
TWE A
0 1
2 NOT ACK ACK
$68
TWDR TWDR TWDR TWDR
X X
0 1
NOT ACK ACK
$70
X X
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 1
NOT ACK ACK
$78
TWDR TWDR TWDR TWDR
X X X X 0 0 1
0 1
NOT ACK ACK
$80
0 1
NOT ACK ACK
$88
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
1 0 1 1
203
2467L-AVR-05/04
Table 90.
$90
ACK NOT ACK
r
X X 0 0 1
0 0 0 0 0
1 1 1 1 1
0 1
NOT ACK ACK
$98
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
1 0 1 1
$A0
STOP START
r
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
1 0 1 1
204
ATmega128
2467L-AVR-05/04
ATmega128
Figure 101.
Reception of the own slave address and one or more data bytes. All are acknowledged
S
SLA
W
A
DATA
A
DATA
A
P or S
$60
Last data byte received is not acknowledged
$80
$80
$A0
A
P or S
$88
Arbitration lost as master and addressed as slave
A
$68
Reception of the general call address and one or more data bytes
General Call
A
DATA
A
DATA
A
P or S
$70
Last data byte received is not acknowledged
$90
$90
$A0
A
P or S
$98
Arbitration lost as master and addressed as slave by general call
A
$78
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
Figure 102 "0" Figure 102.
VCC
Device 1
SLAVE TRANSMITTER
Device 2
MASTER RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
205
2467L-AVR-05/04
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
7 TWI LSB TWI $00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) "1" ( ) TWI TWSR Table 91 TWI ( $B0) CPU TWEA TWI $C0 $C8 "1" ( ACK) $C8 TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVR AVR SCL MCU TWDR Table 91.
(TWSR) "0" TWCR 22 / TWDR STA STO TWIN T TWE A 2
206
ATmega128
2467L-AVR-05/04
ATmega128
Table 91.
$A8
SLA+R ACK

X X
0 0
1 1
0 1
NOT ACK ACK
$B0
SLA+R/W SLA+R ACK TWDR ACK

X X
0 0
1 1
0 1
NOT ACK ACK
$B8
X X
0 0
1 1
0 1
NOT ACK ACK
$C0
TWDR NOT ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
TWDR
1 0 1 1
TWDR
$C8
TWDR (TWAE = "0"); ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
TWDR
1 0 1 1
TWDR
207
2467L-AVR-05/04
Figure 103.
Reception of the own slave address and one or more data bytes
S
SLA
R
A
DATA
A
DATA
A
P or S
$A8
Arbitration lost as master and addressed as slave
$B8
$C0
A
$B0
Last data byte transmitted. Switched to not addressed slave (TWEA = '0')
A
All 1's
P or S
$C8
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
TWI Table 92 $F8 TWINT "0" TWI $00 START STOP ACK START STOP TWINT TWSTO "1" TWINT TWI TWSTO (TWCR ) SDA SCL STOP
Table 92.
(TWSR) "0"
0xF8
TWCR 2 2 TWINT = "0" START STOP / TWDR TWDR TWDR
0
STA
STO
TWIN T
TWE A
2
TWCR
0x00
1
1
X
STOP TWSTO
TWI
TWI EEPROM 1. 2. EEPROM 3. 4. MT MR EEPROM
208
ATmega128
2467L-AVR-05/04
ATmega128
REPEATED START REPEATED START Figure 104. TWI EEPROM
Master Transmitter Master Receiver
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
S = START Transmitted from master to slave
Rs = REPEATED START Transmitted from slave to master
P = STOP
TWI Figure 105.
VCC
Device 1
MASTER TRANSMITTER
Device 2
MASTER TRANSMITTER
Device 3
SLAVE RECEIVER
........
Device n
R1
R2
SDA
SCL
* * READ/WRITE SDA "0" START SLA SDA "0" SLA SR ST SLA READ/WRITE START
*
Figure 106 TWI
209
2467L-AVR-05/04
Figure 106.
START SLA Data STOP
Arbitration lost in SLA
Arbitration lost in Data
Own Address / General Call received
No
38
TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free
Yes Write 68/78
Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
Direction
Read B0
Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received
210
ATmega128
2467L-AVR-05/04
ATmega128
AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 107 Figure 107.
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER 1) OUTPUT
Notes:
1. P 212Table 94 2. P 2Figure 1 P 69Table 30
IO SFIOR
Bit / 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR0 R/W 0 0 PSR321 R/W 0 SFIOR
* Bit 3 - ACME: "1" ADC (ADCSRA ADEN "0") ADC "0" AIN1 P 211" " ACSR
Bit /
7 ACD R/W 0
6 ACBG R/W 0
5 ACO R N/A
4 ACI R/W 0
3 ACIE R/W 0
2 ACIC R/W 0
1 ACIS1 R/W 0
0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG:
211
2467L-AVR-05/04
ACBG AIN0 P 50 " " * Bit 5 - ACO: ACO 1-2 * Bit 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI "1" * Bit 3 - ACIE: ACIE "1" I * Bit 2 - ACIC: ACIC T/C1 T/C1 ACIC "0" T/C1 TIMSK TICIE1 * Bits 1, 0 - ACIS1, ACIS0: Table 93 Table 93. ACIS1/ACIS0
ACIS1 0 0 1 1 ACIS0 0 1 0 1
ACIS1/ACIS0 ACSR
ADC7..0 ADC ADC (SFIOR ACME) ADC (ADCSRA ADEN 0) ADMUX MUX2..0 Table 94 ACME ADEN AIN1 Table 94.
ACME 0 1 1 1 1 1 1 ADEN x 1 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4
212
ATmega128
2467L-AVR-05/04
ATmega128
Table 94.
ACME 1 1 1 ADEN 0 0 0 MUX2..0 101 110 111 ADC5 ADC6 ADC7
213
2467L-AVR-05/04
* * * * * * * * * * * * * *
10 0.5 LSB 2 LSB 13 - 260 s 15 kSPS 8 7 2 10x 200x ADC 0 - VCC ADC 2.56V ADC ADC
ATmega128 10 ADC ADC 8 A 8 0V (GND) 16 (ADC1 ADC0 ADC3 ADC2) A/D 0 dB (1x) 20 dB (10x) 46 dB (200x) (ADC1) ADC 1x 10x 8 200x 7 ADC ADC ADC Figure 108 ADC AVCC AVCC VCC 0.3V P 219"ADC " 2.56V AVCC AREF
214
ATmega128
2467L-AVR-05/04
ATmega128
Figure 108.
ADC CONVERSION COMPLETE IRQ
8-BIT DATA BUS
ADIF ADIE
15 ADC DATA REGISTER (ADCH/ADCL)
ADPS0 ADC[9:0]
0
ADC MULTIPLEXER SELECT (ADMUX)
ADLAR MUX3 MUX2 MUX1 REFS1 REFS0 MUX4 MUX0
ADC CTRL. & STATUS REGISTER (ADCSRA)
ADPS2 ADPS1 ADFR ADEN
ADSC
ADIF
PRESCALER MUX DECODER
CHANNEL SELECTION GAIN SELECTION
CONVERSION LOGIC
AVCC
INTERNAL 2.56V REFERENCE AREF
10-BIT DAC
SAMPLE & HOLD COMPARATOR +
AGND
BANDGAP REFERENCE
ADC7
SINGLE ENDED / DIFFERENTIAL SELECTION
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 + POS. INPUT MUX
ADC MULTIPLEXER OUTPUT
GAIN AMPLIFIER
NEG. INPUT MUX
215
2467L-AVR-05/04
ADC 10 GND AREF 1 LSB ADMUX REFSn AVCC 2.56V AREF AREF ADMUX MUX ADC GND ADC ADC ADC ADCSRA ADEN ADC ADEN ADEN ADC ADC ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC
ADC ADSC "1" ADC ADC ADCSRAADFR1 ADCSRAADSC1 ADC ADC ADIF
Figure 109. ADC
ADEN CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
50 kHz 200 kHz 10 200 kHz
216
ATmega128
2467L-AVR-05/04
CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
ATmega128
SFIOR ADHSM ADC ADC 100 kHz CPU ADC ADCSRA ADPS ADCSRA ADEN ADC ADEN 1 ADEN ADCSRA ADSC ADC P 217" " 13 ADC ADC (ADCSRA ADEN ) 25 ADC ADC 1.5 ADC ADC 13.5 ADC ADC ADC ADIF ADSC ( ) ADSC ADC ADSC 1 Table 95 Figure 110. ADC ( )
First Conversion Next Conversion
Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
MSB of Result LSB of Result
MUX and REFS Update
Sample &Hold
Conversion Complete
MUX and REFS Update
Figure 111. ADC
One Conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 Next Conversion 1 2 3
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
217
2467L-AVR-05/04
Figure 112. ADC
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
Table 95. ADC
& ( ) 14.5 1.5 1.5/2.5 ( ) 25 13 13/14
CKADC2 ADC ADC CKADC2 CKADC2 ( )(13 ADC ) CKADC2 14 ADC CKADC2 ( ) 14 ADC 4 kHz ADC ADC 6 s 12 kSPS
ADMUXMUXnREFS1:0 CPU ADC (ADCSRA ADIF ) ADSC ADSC ADC ADMUX 125 s 125 s
218
ATmega128
2467L-AVR-05/04
ATmega128
ADC ( ADMUX REFS1:0 ) JTAG PORTF7:4 ADC P 77Table 42, " F ,"
219
2467L-AVR-05/04
ADC
ADSC ADC ADSC ADC
ADC
ADC(VREF)ADC VREF 0x3FF VREF AVCC 2.56V AREF AVCCADC 2.56V(VBG) AREF ADC AREF VREF AREF VREF AREF AREF AVCC 1.1V ADC P 306Table 136 AVCC
ADC
ADC CPUI/O ADC 1. ADC ADC 2. ADC ( ) CPU ADC 3. ADC ADCCPU ADC ADC CPU ADC ADC CPU ADC ADC ADEN ADC ADC
Figure 113. ADC ADCn ADC ( ) (S/H) ADC10 k S/H S/H k (fADC/2) ADC
220
ATmega128
2467L-AVR-05/04
ATmega128
Figure 113.
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
(EMI) 1. 2. Figure 114 AVCC LC VCC 3. ADC CPU 4. ADC[3..0] Figure 114. ADC
(AD0) PA0 VCC GND (ADC7) PF7 (ADC6) PF6 (ADC5) PF5 (ADC4) PF4 (ADC3) PF3 (ADC2) PF2 (ADC1) PF1 (ADC0) PF0
10
51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
AREF GND AVCC
100nF Analog Ground Plane
PEN
221
2467L-AVR-05/04
1 LSB n ADC GND VREF 2n (LSBs) 0 2n-1 * (0x000 0x001) (0.5 LSB) 0 LSB
ADC
Figure 115.
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
*
(0x3FE 0x3FF) ( 1.5 LSB) 0 LSB
222
ATmega128
2467L-AVR-05/04
ATmega128
Figure 116.
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
*
(INL) INL0 LSB
Figure 117. (INL)
Output Code
INL
Ideal ADC Actual ADC
VREF
Input Voltage
223
2467L-AVR-05/04
*
(DNL) ( ) (1 LSB) 0 LSB
Figure 118. (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* *
(1 LSB) 0.5 LSB ( ) 0.5 LSB
224
ATmega128
2467L-AVR-05/04
ATmega128
ADC
(ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF IN REF (P 226Table 97 P 227Table V V 98 ) 0x000 0x3FF 1LSB ( V POS - V NEG ) GAIN 512 ADC = --------------------------------------------------------------------------V REF VPOS VNEG GAIN VREF 2 0x200 (-512d) 0x1FF (+511d) MSB(ADCH ADC9) 1 Figure 119 Table 96 GAIN VREF (ADCn - ADCm) Figure 119.
Output Code 0x1FF
0x000 - V REF/GAIN 0x3FF 0 VREF/GAIN Differential Input Voltage (Volts)
0x200
225
2467L-AVR-05/04
Table 96.
VADCn VADCm + VREF /GAIN VADCm + 511/512 VREF /GAIN VADCm + 511/512 VREF /GAIN ... VADCm + 1/512 VREF /GAIN VADCm VADCm - 1/512 VREF /GAIN ... VADCm - 511/512 VREF /GAIN VADCm - VREF /GAIN 0x1FF 0x1FF 0x1FE ... 0x001 0x000 0x3FF ... 0x201 0x200 511 511 510 ... 1 0 -1 ... -511 -512
ADMUX = 0xED (ADC3 - ADC2 10x 2.56V ) ADC3 300 mV ADC2 500 mV ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ADCL 0x00 ADCH 0x9C ADLAR 0 ADCL = 0x70 ADCH = 0x02 ADC ADMUX
Bit / 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX
* Bit 7:6 - REFS1:0: Table 97 (ADCSRA ADIF ) AREF Table 97. ADC
REFS1 0 0 1 1 REFS0 0 1 0 1 AREF Vref AVCC AREF 2.56V AREF
*
Bit 5 - ADLAR: ADC
ADLARADCADC ADLAR ADLAR ADC P 228"ADC ADCL ADCH" * Bits 4:0 - MUX4:0:
226
ATmega128
2467L-AVR-05/04
ATmega128
ADC Table 98 (ADCSRA ADIF ) Table 98.
MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1.23V (VBG) 0V (GND) N/A ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC0 ADC1 ADC2 ADC3 ADC2 ADC3 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 N/A ADC0 ADC0 ADC0 ADC0 ADC2 ADC2 ADC2 ADC2 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 10x 10x 200x 200x 10x 10x 200x 200x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x N/A
227
2467L-AVR-05/04
ADC A ADCSRA
Bit /
7 ADEN R/W 0
6 ADSC R/W 0
5 ADFR R/W 0
4 ADIF R/W 0
3 ADIE R/W 0
2 ADPS2 R/W 0
1 ADPS1 R/W 0
0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC ADENADC ADC ADC * Bit 6 - ADSC: ADC ADSC ADC ADSC ( ADC ADSC ADC ADSC) 25 ADC 13 ADC ADSC "1"ADSC * Bit 5 - ADFR: ADC 1 ADC ADC 0 * Bit 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSRA SBI CBI * Bit 3 - ADIE: ADC ADIE SREG I ADC * Bits 2:0 - ADPS2:0: ADC XTAL ADC Table 99. ADC
ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128
228
ATmega128
2467L-AVR-05/04
ATmega128
ADC ADCL ADCH ADLAR = 0:
Bit 15 - ADC7 7 / R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
ADLAR = 1:
Bit 15 ADC9 ADC1 7 / R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
ADC 2 ADCL ADC ADCH 8 ADCH ADCL ADCH ADMUX ADLAR MUXn ADLAR 1 ( ) * ADC9:0: ADC ADC P 224"ADC "
229
2467L-AVR-05/04
JTAG OCD(On-chip Debug)
* IEEE 1149.1 JTAG * IEEE 1149.1 (JTAG) *
- - SRAM - - - EEPROM Flash * OCD - AVR Break - - - - * JTAG Flash EEPROM * AVR Studio OCD
IEEE 1149.1 AVR JTAG * * * JTAG PCB OCD
JTAG JTAG P 286" JTAG " P 235"IEEE 1149.1 (JTAG) " OCD JTAG ATMEL ATMEL JTAGICE Figure 120JTAGOCDTAPTCKTMS TAP JTAG TDI( ) TDO( ) ( ) JTAG ID (Bypass) JTAG ( ) OCD
TAP
JTAG JTAG TAP * * * * TMS TAP TCK JTAG TCK TDI --() TDO --
ATmega128 IEEE 1149.1 TAP TRST - Test ReSeT JTAGEN TAP I/O TAP JTAGEN MCUCSR JTD TAP JTAG JTAG TAP TAP (TDO) JTAGEN 230
ATmega128
2467L-AVR-05/04
ATmega128
OCD RESET RESET Figure 120.
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI TDO TCK TMS
TAP CONTROLLER
JTAG PROGRAMMING INTERFACE
AVR CPU INSTRUCTION REGISTER ID REGISTER M U X BYPASS REGISTER FLASH MEMORY Address Data INTERNAL SCAN CHAIN PC Instruction
BREAKPOINT UNIT
ANALOG PERIPHERIAL UNITS
DIGITAL PERIPHERAL UNITS
BREAKPOINT SCAN CHAIN ADDRESS DECODER JTAG / AVR CORE COMMUNICATION INTERFACE
I/O PORT n
231
2467L-AVR-05/04
Control & Clock lines
OCD STATUS AND CONTROL
Analog inputs
FLOW CONTROL UNIT
Figure 121. TAP
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
TAP
TAP16 JTAGOCD Figure 121 TCK TMS ( 0/1 ) Test-Logic-Reset LSB / Run-Test/Idle JTAG * TCK TMS 1 1 0 0 - Shift-IR TMS TCK TDI 4 JTAG 3 JTAG TMS TDI JTAG JTAG IR 0x01 TDO JTAG TDI TDO
232
ATmega128
2467L-AVR-05/04
ATmega128
* TMS 110 Run-Test/Idle Update-IR Exit-IR Pause-IR Exit2-IR TCK TMS 100 - Shift-DR TCK TDI ( JTAG JTAG ) Shift-DR TMS Capture-DR TDO TCK TMS 100 - Shift-DR TCK TDI ( JTAG JTAG ) Shift-DR TMS Capture-DR TDO TMS 110 Run-Test/Idle Update-DR Exit-IR PauseIR Exit2-IR
*
*
*
JTAG Run-Test/Idle JTAG Run-Test/Idle Idle
Note: TAP Test-Logic-Reset TMS 5 TCK
JTAG P 234" "
OCD
P 235"IEEE 1149.1 (JTAG) " Figure 120 OCD * * * AVR CPU CPU JTAG
/ AVR CPU AVR CPU I/O I/O CPU JTAG 4 * * * * * 4 3 + 1 2 + 2 2 + 1 ( ) 2 + 1 ( )
AVR Studio(R) OCD P 233"OCD JTAG " JTAG JTAG JTAGEN OCD OCD OCD
233
2467L-AVR-05/04
AVR StudioAVR JTAGOCD AVR ICE AVR AVR Studio Atmel AVR C C AVR Studio Microsoft Windows(R) 95/98/2000 Microsoft WindowsNT(R) AVR Studio AVR Studio User Guide AVR Studio BREAK ( )
OCD JTAG
PRIVATE0; $8 PRIVATE1; $9 PRIVATE2; $A PRIVATE3; $B
OCD JTAG JTAG OCD JTAG OCD JTAG OCD JTAG OCD
234
ATmega128
2467L-AVR-05/04
ATmega128
I/O OCD
OCD OCDR
Bit / 7 MSB/IDRD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCDR
OCDR CPU - I/O - IDRD CPU OCDR 7 OCDR MSB IDRD IDRD AVR I/O OCDEN OCDR I/O
JTAG
JTAG AVR JTAG TCK TMS TDI TDO JTAG JTAGEN MCUSR JTD JTAG JTAG * * * * Flash EEPROM
LB1 LB2 OCDEN JTAG JTAG P 286" JTAG "
* * IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993 Colin Maunder: The Board Designers Guide to Testable Logic Circuits, AddisonWesley, 1992
235
2467L-AVR-05/04
IEEE 1149.1 (JTAG)
* * * * *
IEEE 1149.1 JTAG JTAG IDCODE AVR_RESET AVR
AVR I/O JTAG IC TDI/TDO 4 TAP PCB IEEE 1149.1 JTAG : IDCODE BYPASS SAMPLE/PRELOAD EXTEST AVRJTAGAVR_RESETPCB IDCODE JTAG ID AVR BYPASS AVR AVR RESET AVR AVR_RESET EXTEST EXTEST JTAG IR EXTEST SAMPLE/PRELOAD SAMPLE/PRELOAD AVR " " JTAG TAP JTAG JTAGEN MCUCSR JTD JTAG JTAG TCK
* * * * Bypass
236
ATmega128
2467L-AVR-05/04
ATmega128
Bypass Bypass TDI TDO Capture-DR 0 Bypass Figure 122 Figure 122.
MSB Bit ID 31 4 bits 28 27 16 bits 12 11 ID 11 bits 1 LSB 0 1 1-bit

4 A 0x0 B 0x1 16 ATmega128 JTAG Table 100 Table 100. AVR JTAG
ATmega128 JTAG (Hex) 0x9702
ID
ID 11 ATMEL JTAG ID Table 101 Table 101. ID
ATMEL JTAG ID (Hex) 0x01F
AVR JTAG HIGHZ 0 AVR AVR AVR CPU Figure 123
237
2467L-AVR-05/04
Figure 123.
To TDO
From Other Internal and External Reset Sources From TDI Internal Reset
D
Q
ClockDR * AVR_RESET
AVR I/O P 238" "
JTAG
4 16 JTAG HIGHZ AVR_RESET LSB / (OPCODE) HEX TDI TDO
EXTEST; $0
JTAG AVR EXTEST JTAG IR * * * Capture-DR ( ) Shift-DR TCK Update-DR
IDCODE; $1
JTAG 32 ID ID JEDEC ID * * Capture-DR IDCODE Shift-DR IDCODE TCK
SAMPLE_PRELOAD; $2
JTAG / " "
238
ATmega128
2467L-AVR-05/04
ATmega128
* * * AVR_RESET; $C Capture-DR ( ) Shift-DR TCK Update-DR
AVR JTAG AVR JTAG TAP 1 * Shift-DR TCK
BYPASS; $F
JTAG Bypass * * Capture-DR `0' Bypass Shift-DR TDI TDO Bypass
I/O
MCU MCUCSR MCU MCU
Bit / 7 JTD R/W 0 6 - R 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUCSR
* Bit 7 - JTD: JTAG '0' JTAG JTAGEN JTAG JTAG JTAG JTAG JTAG JTD '1' JTAG TDO * Bit 4 - JTRF: JTAG JTAG '0' AVR_RESET JTRF '0'
AVR I/O Figure 124 - PUExn - OCxn - ODxn - IDxn Figure 125 P 61"I/O " Figure 124 Figure 125
239
2467L-AVR-05/04
- ID PINxn ( ID ) PORT - DD - PUExn - PUD * DDxn * PORTxn Figure 125 Figure 124. .
ShiftDR To Next Cell EXTEST Vcc
Pullup Enable (PUE) FF2 0 D 1 G Q D Q LD2
0 1
Output Control (OC) FF1 0 D 1 G Q D Q LD1 0 1
Output Data (OD)
0 1 0
FF0 D 1 Q
LD0 D G Q
0 Port Pin (PXn) 1
Input Data (ID)
From Last Cell
ClockDR
UpdateDR
240
ATmega128
2467L-AVR-05/04
ATmega128
Figure 125.
See Boundary-Scan description for details!
PUExn
PUD
Q
D
DDxn
Q CLR
OCxn
RESET
WDx
RDx
Pxn
Q
D
ODxn IDxn SLEEP
PORTxn
Q CLR
WPx RESET RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn
L
Q
Q
CLK I/O
PUD: PUExn: OCxn: ODxn: IDxn: SLEEP:
PULLUP DISABLE PULLUP ENABLE for pin Pxn OUTPUT CONTROL for pin Pxn OUTPUT DATA to pin Pxn INPUT DATA from pin Pxn SLEEP CONTROL
WDx: RDx: WPx: RRx: RPx: CLK I/O :
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN I/O CLOCK
TWI
SCL SDA - TWIEN Figure 126 TWIEN Figure 130
Notes: 1. 50ns TWIEN 2. OC TWIEN
DATA BUS
241
2467L-AVR-05/04
Figure 126.
PUExn
OCxn ODxn
Pxn
TWIEN
SRC
Slew-rate limited IDxn
RESET
RESET5V12V Figure 127 5V RSTT 12V RSTHV Figure 127.
To next cell
ShiftDR
From system pin
To system logic
FF1
0 D 1 Q
From previous cell
ClockDR
AVR RC RC ( ) Figure 128 / RC
242
ATmega128
2467L-AVR-05/04
ATmega128
Figure 128.
XTAL1/TOSC1 XTAL2/TOSC2
ShiftDR
To Next Cell
EXTEST
Oscillator
ENABLE OUTPUT
ShiftDR
To next cell
From Digital Logic
0 1 0 D 1 G Q D Q
To System Logic
FF1
0 D 1 Q
From Previous Cell
ClockDR
UpdateDR From Previous Cell ClockDR
Table 102XTAL1 XTAL1/XTAL2 32 kHz Table 102. (1)(2)(3)
EXTCLKEN OSCON RCOSCEN OSC32EN TOSKON Notes: EXTCLK (XTAL1) OSCCK RCCK OSC32CK TOSCK RC 32 kHz 0 0 1 0 0
1. 2. JTAG TCK 3. INTCAP XTAL
Figure 129 Figure 130 Table 103
243
2467L-AVR-05/04
Figure 129.
BANDGAP REFERENCE ACBG
ACO
AC_IDLE
ACME ADCEN ADC MULTIPLEXER OUTPUT
Figure 130. ADC
To Next Cell
ShiftDR
EXTEST
From Digital Logic/ From Analog Ciruitry 0 D 1 G Q D Q
0 1
To Analog Circuitry/ To Digital Logic
From Previous Cell
ClockDR
UpdateDR
244
ATmega128
2467L-AVR-05/04
ATmega128
Table 103.
AC_IDLE ACO '1' 1 C 0 C 0
ACME
'1' ADC
C C
ACBG
0
ADC
Figure 131ADC Figure 127 ADC Figure 131.
VCCREN
AREF
IREFEN
To Comparator
2.56V ref
MUXEN_7 ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADC_4
PASSEN
SCTEST
ADCBGEN
EXTCH MUXEN_3 ADC_3 MUXEN_2 ADC_2 MUXEN_1 ADC_1 MUXEN_0 ADC_0 NEGSEL_2
ADC_2
1.22V ref
PRECH
PRECH AREF
AREF
DACOUT
DAC_9..0
10-bit DAC + COMP
COMP
G10
+
G20 ADCEN ACTEN
+
-
10x
-
20x
-
HOLD GNDEN
NEGSEL_1
ADC_1
NEGSEL_0
ADC_0
ST ACLK AMPEN
Table 104
245
2467L-AVR-05/04
Table 104. ADC
COMP ACLK ACTEN ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH G10 G20 GNDEN HOLD ADC DAC 9 DAC 8 DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 ADC 0 - 3 10x 20x '1' & '0' '1' ACLK DAC AREF 7 6 5 4 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 CPU ADC 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
IREFEN MUXEN_7 MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3

0 0 0 0 0 0
0 0 0 0 0 0
246
ATmega128
2467L-AVR-05/04
ATmega128
Table 104. ADC (Continued)
MUXEN_2 MUXEN_1 MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST 2 1 0 2 1 0 ( ) TEST 10x ADC_4 AMPEN ACLK Vcc ADC 0 0 1 0 0 0 1 1 0 CPU ADC 0 0 1 0 0 0 1 1 0
ST
0
0
VCCREN Note:
0
0
Figure 131 Figure 131 S&H ADC
ADC Table 104 ADC (ADHSM) AVR ADC Figure 131 : DAC[9:0] DAC[9:0] ADC ADC * * * ADC ADC""(10) ADC 200ns " " HOLD ( ) DAC 0x200
247
2467L-AVR-05/04
5.0V AREF VCC ADC 3 1.5V 5%
The lower limit is: The upper limit is: 1024 1,5V 0,95 5V = 291 = 0x123 1024 1,5V 1,05 5V = 323 = 0x143
Table 105 Table 104 Table 105 DAC " " JTAG Table 105. ADC
PA3. 1 2 3 4 5 6 7 8 9 10 11 COMP 1 COMP 0 SAMPLE_ PRELOAD EXTEST ADCEN 1 1 1 1 1 1 1 1 1 1 1 DAC 0x200 0x200 0x200 0x123 0x123 0x200 0x200 0x200 0x143 0x143 0x200 MUXEN 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 HOLD 1 0 1 1 1 1 0 1 1 1 1 PRECH 1 1 1 1 0 1 1 1 1 0 1 PA3. 0 0 0 0 0 0 0 0 0 0 0 PA3. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HOLD TCK 5 HOLD TCK 5 thold,max
248
ATmega128
2467L-AVR-05/04
ATmega128
ATmega128
TDI TDO Table 106 Bit 0 LSB ( / ) A Figure 124 PXn.Data FF0 PXn.Control FF1 PXn. Pullup_enable FF2 C 2 4 3 5 JTAG TAP Table 106. ATmega128
204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 AC_IDLE ACO ACME AINBG COMP PRIVATE_SIGNAL1 ACLK ACTEN PRIVATE_SIGNAL1(2) ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH G10 G20 GNDEN HOLD IREFEN MUXEN_7
(1)

ADC
249
2467L-AVR-05/04
Table 106. ATmega128
175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3 MUXEN_2 MUXEN_1 MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST ST VCCREN PEN PE0.Data PE0.Control PE0.Pullup_Enable PE1.Data PE1.Control PE1.Pullup_Enable PE2.Data PE2.Control PE2.Pullup_Enable PE3.Data PE3.Control PE3.Pullup_Enable PE4.Data PE4.Control PE4.Pullup_Enable PE5.Data PE5.Control PE5.Pullup_Enable PE6.Data PE6.Control ( ) E ADC
250
ATmega128
2467L-AVR-05/04
ATmega128
Table 106. ATmega128
139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 PE6.Pullup_Enable PE7.Data PE7.Control PE7.Pullup_Enable PB0.Data PB0.Control PB0.Pullup_Enable PB1.Data PB1.Control PB1.Pullup_Enable PB2.Data PB2.Control PB2.Pullup_Enable PB3.Data PB3.Control PB3.Pullup_Enable PB4.Data PB4.Control PB4.Pullup_Enable PB5.Data PB5.Control PB5.Pullup_Enable PB6.Data PB6.Control PB6.Pullup_Enable PB7.Data PB7.Control PB7.Pullup_Enable PG3.Data PG3.Control PG3.Pullup_Enable PG4.Data PG4.Control PG4.Pullup_Enable TOSC TOSCON 32 kHz G B E
251
2467L-AVR-05/04
Table 106. ATmega128
103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 RSTT RSTHV EXTCLKEN OSCON RCOSCEN OSC32EN EXTCLK (XTAL1) OSCCK RCCK OSC32CK TWIEN PD0.Data PD0.Control PD0.Pullup_Enable PD1.Data PD1.Control PD1.Pullup_Enable PD2.Data PD2.Control PD2.Pullup_Enable PD3.Data PD3.Control PD3.Pullup_Enable PD4.Data PD4.Control PD4.Pullup_Enable PD5.Data PD5.Control PD5.Pullup_Enable PD6.Data PD6.Control PD6.Pullup_Enable PD7.Data PD7.Control PD7.Pullup_Enable PG0.Data G TWI D ( ) ( ) /
252
ATmega128
2467L-AVR-05/04
ATmega128
Table 106. ATmega128
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PG0.Control PG0.Pullup_Enable PG1.Data PG1.Control PG1.Pullup_Enable PC0.Data PC0.Control PC0.Pullup_Enable PC1.Data PC1.Control PC1.Pullup_Enable PC2.Data PC2.Control PC2.Pullup_Enable PC3.Data PC3.Control PC3.Pullup_Enable PC4.Data PC4.Control PC4.Pullup_Enable PC5.Data PC5.Control PC5.Pullup_Enable PC6.Data PC6.Control PC6.Pullup_Enable PC7.Data PC7.Control PC7.Pullup_Enable PG2.Data PG2.Control PG2.Pullup_Enable PA7.Data PA7.Control PA7.Pullup_Enable PA6.Data A G C G
253
2467L-AVR-05/04
Table 106. ATmega128
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Notes: PA6.Control PA6.Pullup_Enable PA5.Data PA5.Control PA5.Pullup_Enable PA4.Data PA4.Control PA4.Pullup_Enable PA3.Data PA3.Control PA3.Pullup_Enable PA2.Data PA2.Control PA2.Pullup_Enable PA1.Data PA1.Control PA1.Pullup_Enable PA0.Data PA0.Control PA0.Pullup_Enable PF3.Data PF3.Control PF3.Pullup_Enable PF2.Data PF2.Control PF2.Pullup_Enable PF1.Data PF1.Control PF1.Pullup_Enable PF0.Data PF0.Control PF0.Pullup_Enable 1. PRIVATE_SIGNAL1 0 2. PRIVATE_SIGNAL2 0 F A
254
ATmega128
2467L-AVR-05/04
ATmega128
(BSDL)
255
2467L-AVR-05/04
- (RWW, Read-WhileWrite)
Boot Loader MCU - (ReadWhile-Write RWW) MCU Flash Boot Loader Boot Loader ( ) Flash Boot Loader Flash Boot Loader Boot Loader Boot Loader Boot Loader * * * * * * *
RWW Boot Loader ( Boot ) (1) RWW 1. Flash ( P 273Table 123 )
Note:
Flash Flash Boot Loader ( Figure 133) BOOTSZ P 266Table Figure 133 Flash
Flash Boot (Boot 0) P 258Table SPM Boot Loader Boot Loader BLS BLS SPM SPM Flash BLS Boot Loader Boot Loader (Boot 1) P 259Table 109 CPU RWW CPU Boot Loader BOOTSZ Flash ---- - (RWW) - (NRWW) RWW NRWW P 266Table Note: P 258Figure 133 * * RWW NRWW NRWW CPU
(Boot Loader Section) BLS
RWW Flash RWW Flash
Boot Loader RWW "RWW " ( ) Boot Loader RWW Boot Loader RWW Flash NRWW Flash RWW RWW ( call/jmp/lpm ) Boot Loader Boot Loader NRWW RWW (SPMCSR) RWW RWWSB RWW RWWSB RWWSB P 258 " SPMCSR"
256
ATmega128
2467L-AVR-05/04
ATmega128
RWW NRWW Boot Loader RWW NRWW Boot Loader NRWW CPU Table 107. RWW
Z ? RWW NRWW ? NRWW CPU ? RWW ?
Figure 132. RWW NRWW
Read-While-Write (RWW) Section
Z-pointer Addresses RWW Section
Z-pointer Addresses NRWW Section
No Read-While-Write (NRWW) Section
CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation
257
2467L-AVR-05/04
Figure 133. (1)
Program Memory BOOTSZ = '11' $0000
Read-While-Write Section Read-While-Write Section
Program Memory BOOTSZ = '10' $0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' $0000
Read-While-Write Section Read-While-Write Section
$0000
Application Flash Section
Application flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. P 266Table
Boot Loader Flash Boot Loader Boot * * * * Flash MCU MCU Boot Loader Flash MCU Flash MCU Flash
Table 108 Table 109 Boot ( 2) SPM Flash / ( 1) LPM/SPM /
258
ATmega128
2467L-AVR-05/04
ATmega128
Table 108. Boot 0 ( )(1)
BLB0 1 2 BLB02 1 1 BLB01 1 0 SPM/LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader
3
0
0
4 Note:
0
1
1. "1" "0"
Table 109. Boot 1 (Boot Loader )(1)
BLB1 1 2 BLB12 1 1 BLB11 1 0 SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader
3
0
0
4 Note:
0
1
1. "1" "0"
Boot Loader USART SPI Boot Boot Boot Loader MCU Boot Boot Table 110. Boot (1)
BOOTRST 1 0 Note: Reset Vector = ( $0000) Reset Vector = Boot Loader ( P 266Table 112 )
1. "1" , "0"
SPMCSR
Boot Loader
Bit / 7 SPMIE R/W 0 6 RWWSB R 0 5 - R 0 4 RWWSRE R/W 0 3 BLBSET R/W 0 2 PGWRT R/W 0 1 PGERS R/W 0 0 SPMEN R/W 0 SPMCSR
* Bit 7 - SPMIE: SPM
259
2467L-AVR-05/04
SPMIE I SPM SPMCSR SPMEN SPM * Bit 6 - RWWSB:RWW RWW ( ) RWWSB 1 RWWSB RWW RWWSRE 1 RWWSB RWWSB * Bit 5 - Res: ATmega128 "0" * Bit 4 - RWWSRE: RWW RWW() RWW(RWWSB"1") (SPMEN)RWW RWWSRE SPMEN"1" SPMRWW Flash (SPMEN ),RWW Flash RWWSRE Flash * Bit 3 - BLBSET: Boot SPMEN SPM R0 Boot R1 Z SPM BLBSET SPMCSR BLBSET SPMEN LPM ( Z Z0) P 262" " * Bit 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU * Bit 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * Bit 0 - SPMEN: SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN 1 "10001" "01001" "00101" "00011" "00001"
Flash
ZRAMPZSPMRAMPZ P 11 "RAMZ RAMPZ"
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
260
ATmega128
2467L-AVR-05/04
ATmega128
Flash (P 273Table 123 ) Figure 134 Boot Loader Z /RAMPZ Z /RAMPZ SPM Boot Loader Z /RAMPZ (E)LPM Z /RAMPZ Z LSB ( Z0) Figure 134. SPM (1)
RAMPZ
BIT 15 ZPCMSB
ZPAGEMSB
10 0 Z - REGISTER
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Notes:
1. Figure 134 P 267Table 114 2. PCPAGE PCWORD P 273Table 124
Flash
SPM 1 * * * * * *
2
( ) Flash 1 Boot Loader - 261
2467L-AVR-05/04
Flash 2 P 263" " SPM Z RAMPZ "X0000011" SPMCSR SPMR1 R0 Z PCPAGE Z * * ( ) RWW NRWW NRWW CPU
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE
Note: SPM EEPROM
Z RAMPZ "X0000101" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU
SPM
SPM SPMCSR SPMEN SPMCSR SPM BLS RWW P 55" " Boot 11 Boot Loader Boot Loader Boot Loader Boot Loader Boot 11 Boot Loader ( ) RWW RWW SPMCSR RWWSB P 55" " BLS RWW RWWSRE 1 RWWSB P 263" "
BLS
RWW
262
ATmega128
2467L-AVR-05/04
ATmega128
SPM Boot Loader R0 "X0001001"SPMCSR SPM Boot Loader MCU Boot Loader
Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
Boot Loader Flash Table 108 Table 109 R0 5..2 0 SPMCSR BLBSET SPMEN SPM Boot Z Z 0x0001( lOck ) R0 7 6 1 0 "1" Flash EEPROM SPMCSR EEPROM Flash SPMCSR EECR EEWE $0001 Z SPMCSRBLBSET SPMEN SPMCSRCPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM
Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
$0000ZSPMCSRBLBSET SPMEN SPMCSR CPU LPM (FLB) P 270Table 119
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
$0003 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (FHB) P 270Table 118
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
0x0002 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (EFB) P 269Table 117 .
Bit Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 EFB1 0 EFB0
"0" "1" Flash VCC CPU Flash Flash Flash
263
2467L-AVR-05/04
Flash Flash CPU Flash ( ) 1. Boot Loader Boot Loader Boot Loader 2. AVR RESET BOD 3. AVR CPU SPMCSR Flash SPM Flash RC Flash Table 111 CPU Flash Table 111. SPM
Flash ( SPM ) 3.7 ms 4.5 ms
;- RAM Flash ; Y RAM ;Z Flash ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24) ; loophi (r25) SPMCSRval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB .org SMALLBOOTSTART Write_page: ; ldi SPMCSRval, (1<264
ATmega128
2467L-AVR-05/04
ATmega128
subi sbci ldi call ZL, low(PAGESIZEB) ; ZH, high(PAGESIZEB) ;PAGESIZEB<=256 SPMCSRval, (1<; RWW ldi SPMCSRval, (1<; ;PAGESIZEB<=256 ;
;PAGESIZEB<=256 subi
; RWW ; RWW Return: lds temp1, SPMCSR sbrs temp1, RWWSB ; RWWSB "1" RWW ret ; RWW ldi SPMCSRval, (1<265
2467L-AVR-05/04
ATmega128
Table 112 Table 114 Table 112. Boot
Boot Loader Flash $FE00 $FFFF $FC00 $FFFF $F800 $FFFF $F000 $FFFF Boot ( Boot Loader ) $FE00 $FC00 $F800 $F000
BOOTSZ1 1 1 0 0
BOOTSZ0 1 0 1 0
Boot 512 1024 2048 4096
4 8 16 32
Flash $0000 $FDFF $0000 $FBFF $0000 $F7FF $0000 $EFFF
$FDFF $FBFF $F7FF $EFFF
Note:
BOOTSZ Figure 133
Table 113. RWW (1)
Flash - (RWW) - (NRWW) Note: 480 32 $0000 - $EFFF $F000 - $FFFF
1. P 256" RWW NRWW" P 255"RWW "
266
ATmega128
2467L-AVR-05/04
ATmega128
Table 114. Figure 134 Z (3)
PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Notes: PC[15:7] PC[6:0] 15 6 Z16(1) Z7 Z16(1):Z7 Z7:Z1 Z (2) ( 16 PC[15:0]) ( 128 7 PC [6:0]). Z PCMSB Z0 ZPCMSB PCMSB + 1 Z PAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0)
1. Z 16 16 RAMPZ 2. Z0 SPM "0" (E)LPM 3. Z P 260" Flash"
267
2467L-AVR-05/04
ATmega128 6 ("0") ("1") Table116 "1" Table 115.
7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 - - Boot Boot Boot Boot 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
"1" "0"
Table 116.
LB 1 2 3 BLB0 1 2 LB2 1 1 0 BLB02 1 1 LB1 1 0 0 BLB01 1 0 SPM (E)LPM SPM SPM Boot Loader (E)LPM Boot Loader Boot Loader (E)LPM Boot Loader SPM/(E)LPM Boot Loader SPI/JTAGFlashEEPROM (1) SPI/JTAGFlashEEPROM (1)
3
0
0
4 BLB1 1
0 BLB12 1
1 BLB11 1
268
ATmega128
2467L-AVR-05/04
ATmega128
Table 116.
2 1 0 SPM Boot Loader SPM Boot Loader (E)LPM Boot Loader Boot Loader (E)LPM Boot Loader Boot Loader
3
0
0
4 Notes:
0
1
1. LB1 LB2 Boot 2. "1" , "0"
ATmega128 Table 117 - Table 119 "0" Table 117.
- - - - - - M103C
(1) (2)
7 6 5 4 3 2 1 0
- - - - - - ATmega103
1 1 1 1 1 1 0 ( ) 1 ( )
WDTON Notes:
1. P 4"ATmega103 ATmega128 " 2. P 52" WDTCR"
269
2467L-AVR-05/04
Table 118.
OCDEN
(4)
7 6 5 4 3 2 1 0
OCD JTAG EEPROM Boot ( Table 112 ) Boot ( Table 112 )
1 ( OCD ) 0 ( JTAG ) 0 ( SPI ) 1 ( ) 1 ( ) EEPROM 0 ( )(3) 0 ( )(3) 1 ( )
JTAGEN SPIEN(1) CKOPT
(2)
EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes: 1. 2. 3. 4.
Table 119.
BODLEVEL BODEN SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: 7 6 5 4 3 2 1 0
SPI SPIEN CKOPT CKSEL P 34" " BOOTSZ1..0 Boot P 266Table 112 JTAGEN OCDEN OCDEN 5. JTAG JTAGEN JTAGTDO
BOD BOD
1 ( ) 1 ( BOD ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 0 ( )(2) 1 ( )(2)
1. SUT1..0 P 38Table 14 2. CKSEL3..0RC1 MHz P 34Table 6
1(LB1) EESAVE Atmel ATmega128 270
ATmega128
2467L-AVR-05/04
ATmega128
1. $000: $1E ( Atmel ) 2. $001: $97 ( 128KB Flash ) 3. $002: $02 ( $001 $97 ATmega128 )
ATmega128 RC 0x000 0x00010x00020x0003 12 48 MHz MHz 1 OSCCAL P 38 " OSCCAL"
271
2467L-AVR-05/04
ATmega128 Flash EEPROM 250 ns
ATmega128 Figure 135 Table 120 XA1/XA0 XTAL1 Table 122 WR OE Table 123 Figure 135.
+5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RESET PA0 XTAL1 GND
PB7 - PB0
VCC +5V AVCC
DATA
Table 120.
RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA PD1 PD2 PD3 PD4 PD5 PD6 PD7 PA0 PB7-0 I/O O I I I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 EEPROM 2("0" , "1" ) (OE )
272
ATmega128
2467L-AVR-05/04
ATmega128
Table 121.
PAGEL XA1 XA0 BS1 Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0
Table 122. XA1 XA0
XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 Flash )
Table 123.
1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM
Table 124. Flash
Flash 64K (128K ) 128 PCWORD PC[6:0] 512 PCPAGE PC[15:7] PCMSB 15
Table 125. EEPROM
EEPROM 4K 8 PCWORD EEA[2:0] 512 PCPAGE EEA[11:3] EEAMSB 8
273
2467L-AVR-05/04
1. VCC GND 4.5 - 5.5V 100 s 2. RESET XTAL1 6 3. P 273Table 121 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable RC XTAL1 1. P 273Table Prog_enable "0000" 2. VCC GND 4.5 - 5.5V RESET 11.5 - 12.5V 3. 100 ns 4. (CKSEL3:0 = 0b0000) 5. RESET 0b0 6. * * * $FF Flash EEPROM( EESAVE ) Flash EEPROM 256
Flash EEPROM(1) Flash / EEPROM
Note: 1. EESAVE EEPRPOM
" " 1. XA1 XA0 10 2. BS1 0 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P 273Table 123 Flash Flash A. " Flash" 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "0001 0000" Flash 4. XTAL1 B. 1. XA1 XA0 "00" 2. BS1 "0" 274
ATmega128
2467L-AVR-05/04
ATmega128
3. DATA ($00 - $FF) 4. XTAL1 C. 1. XA1 XA0 "01" 2. DATA ($00 - $FF) 3. XTAL1 D. 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA ($00 - $FF) 4. XTAL1 E. 1. BS1 "1" 2. PAGEL ( Figure 137 ) F. B E FLASH P 276Figure 136 8 ( < 256) G. 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA ($00 - $FF) 4. XTAL1 H. 1. BS1 = "0" 2. WR RDY/BSY 3. RDY/BSY ( Figure 137 ) I. B H Flash J. 1. 1. XA1 XA0 "10" 2. DATA "0000 0000" 3. XTAL1
275
2467L-AVR-05/04
Figure 136. Flash
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE PCWORD P 273Table 124
Figure 137. Flash
F
A
DATA
0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
C
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
ADDR. LOW DATA LOW
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
"XX" Flash
EEPROM
P 273Table 124 EEPROM EEPROM EEPROM ( P 273" Flash " ) 1. A "0001 0001" 2. G ($00 - $FF) 3. B ($00 - $FF)
276
ATmega128
2467L-AVR-05/04
ATmega128
4. C ($00 - $FF) 5. E ( PAGEL ) K 3 5 L EEPROM 1. BS1 "0" 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure 138) Figure 138. EEPROM
K
A
DATA
0x11
G
B
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
ADDR. HIGH ADDR. LOW
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P 273" Flash " ) 1. A "0000 0010" 2. G ($00 - $FF) 3. B ($00 - $FF) 4. OE "0" BS1 "0" DATA Flash 5. BS1 "1" DATA Flash 6. OE "1"
EEPROM
( P 273" Flash " ) 1. A "0000 0011" 2. G ($00 - $FF) 3. B ($00 - $FF) 4. OE "0" BS1 "0" DATA EEPROM 5. OE "1"
( P 273" Flash " ) 277
2467L-AVR-05/04
1. A "0100 0000" 2. C "0" 3. BS1 "0" BS2 "0" 4. WR RDY/BSY ( P 273" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0" ( P 273" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "0" BS2 "1" 4. WR RDY/BSY 5. BS2 "0" Figure 139.
Write Fuse Low byte A
DATA
$40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
$40
C
DATA XX
C
DATA XX
$40
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
( P 273" Flash " ) 1. A "0010 0000" 2. C. n "0" 3. WR RDY/BSY
( P 273" Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE"0" BS2BS1"1" DATA("0")
278
ATmega128
2467L-AVR-05/04
ATmega128
4. OE BS1 "0" BS2 "1" DATA ("0" ) 5. OE "0" BS2 "0" BS1 "1" DATA ("0" ) 6. OE "1" Figure 140. BS1 BS2
Fuse Low Byte 0
0 Extended Fuse byte BS2 Lock bits 0 1 1 DATA
Fuse high byte BS2
1
BS1
( Flash ) 1. A "0000 1000" 2. B ($00 - $02) 3. OE BS1 "0" DATA 4. OE "1"
( Flash ) 1. A "0000 1000" 2. B 3. OE "0" BS1 "1" DATA 4. OE "1"
Figure 141.
t XLWL XTAL1 t DVXH Data & Contol (DATA, XA0/1, BS1, BS2) t BVPH PAGEL WR RDY/BSY t WLRH t PHPL t WL t PLWL
WLRL WH
t XHXL t XLDX
t PLBX
t BVWL
t WLBX
279
2467L-AVR-05/04
Figure 142.
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
tXLPH tPLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
Figure 141 (tDVXH tXHXL tXLDX)
Figure 143. ( )
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
tBHDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
Figure 141 ( tDVXH tXHXL tXLDX) 11.5 12.5 250 67 200 150 67 0 0 150
Table 126. VCC = 5 V 10%
VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH tPLXH XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL PAGEL XTAL1 V A ns ns ns ns ns ns ns
280
ATmega128
2467L-AVR-05/04
ATmega128
Table 126. VCC = 5 V 10%
tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. 2. PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY (2) XTAL1 OE BS1 DATA OE DATA OE DATA Flash EEPROM tWLRH tWLRH_CE 67 150 67 67 67 67 150 0 3.7 7.5 0 0 250 250 250 1 4.5 9 ns ns ns ns ns ns ns s ms ms ns ns ns ns
RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P 281Table 127 SPI SPI SPI MOSI MISO ATmega128 PDI PDO SPI SPI I/O MOSI/MISO SPI I/OPB2PB3PE0PE1 Table 127 Table 127. SPI
MOSI (PDI) MISO (PDO) SCK PE0 PE1 PB1 I/O I O I
SPI
281
2467L-AVR-05/04
Figure 144. SPI (1)
+2.7 - 5.5V VCC +2.7 - 5.5V(2) PDI PDO SCK PE0 PE1 PB1 XTAL1 AVCC
RESET
GND
Notes:
1. XTAL1 2. VCC - 0.3V < AVCC < VCC + 0.3V AVCC 2.7 - 5.5V
EEPROM MCU EEPROM $FF CKSEL (SCK) fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > SPI ATmega128 SCK ATmega128 SCK Figure 145 ATmega128 ( Table 145 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU PEN SCK "0" RESET PEN SCK 2. 20 ms MOSI 3. ($53) 4 $53 RESET
282
ATmega128
2467L-AVR-05/04
ATmega128
4. Flash P 273Table 124 7 LSB 9 tWD_FLASH ( Table 128) Flash Note: ( ) (Flash EEPROM ) 5. EEPROM EEPROM tWD_EEPROM ( Table 128) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC Flash Flash $FF Flash $FF $FF tWD_FLASH $FF 0xFF tWD_FLASH Table 128 EEPROM $FF $FF $FF $FF EEPROM $FF tWD_EEPROM tWD_EEPROM Table 128
EEPROM
283
2467L-AVR-05/04
Table 128. Flash EEPROM , VCC = 5 V 10%
tWD_FUSE tWD_FLASH tWD_EEPROM tWD_ERASE 5 ms 5 ms 10 ms 10 ms
Figure 145. .SPI
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
284
ATmega128
2467L-AVR-05/04
ATmega128
Table 129. SPI
EEPROM EEPROM Note: 1 1010 1100 1010 1100 0010 H000 0100 H000 0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 1010 1100 0101 0000 0101 0000 0101 1000 0011 1000 2 0101 0011 100x xxxx aaaa aaaa xxxx xxxx aaaa aaaa xxxx aaaa xxxx aaaa 0000 0000 111x xxxx xxxx xxxx 1010 0000 1010 1000 1010 0100 0000 0000 0000 1000 0000 1000 xxxx xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xbbb bbbb bxxx xxxx bbbb bbbb bbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 00bb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxxx xxxx oooo oooo iiii iiii xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii xxxx xxii oooo oooo oooo oooo oooo oooo oooo oooo RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM a:b o "0" "1" P 268Table 115 "0" P 268Table 115 b o "0" "1" P 270Table 119 "0" "1" P 270Table 118 "0" "1" P 270Table 119 "0" "1" P 270Table 119 "0" "1" P 270Table 119 "0" "1" P 270Table 118 b o
a = b = H = 0 - 1 - o = t i = x =
285
2467L-AVR-05/04
SPI
SPI P 303"SPI " JTAG 4 JTAG :TCKTMSTDI TDOreset JTAG JTAGEN MCUCSR JTD JTD 1 reset JTD JTAG JTAG I/O ISP JTAG JTAG LSB /
JTAG
JTAG
4 16 JTAG OPCODE 16 TDI TDO TAPRun-Test/Idle JTAG Figure 146
286
ATmega128
2467L-AVR-05/04
ATmega128
Figure 146.
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
AVR_RESET ($C)
AVR_RESETAVRJTAG AVR TAP 1 1 * Shift-DR TCK
PROG_ENABLE ($4)
PROG_ENABLEAVRJTAG JTAG 16 * * Shift-DR Update-DR
PROG_COMMANDS ($5)
AVR JTAG JTAG 15 * Capture-DR
287
2467L-AVR-05/04
* * * PROG_PAGELOAD ($6)
Shift-DR TCK Update-DR Flash Run-Test/Idle ( Table 130)
AVRJTAG JTAGFlash2048 Flash 8 JTAG Update-DR Shift-DR Flash * Shift-DRFlash TCK
JTAG PROG_PAGELOAD AVR JTAG AVR
Note:
PROG_PAGEREAD ($7)
AVRJTAG JTAGFlash 2056 Flash Flash 8 8 JTAG Capture-DR Shift-DR Flash * Shift-DR Flash TCK TDI
JTAG PROG_PAGEREAD AVRJTAG
Note:
JTAG P 286" JTAG " * * * * * Flash Flash
288
ATmega128
2467L-AVR-05/04
ATmega128
0 0 ( P 34" " ) P 238Figure 123 16 ( 1010_0011_0111_0000) JTAG Figure 147.
TDI
D A T A
$A370
=
D
Q
Programming enable
ClockDR & PROG_ENABLE
TDO
289
2467L-AVR-05/04
15 JTAG Table 130 Figure 149 Figure 148.
TDI
S T R O B E S
A D D R E S S / D A T A
Flash EEPROM Fuses Lock Bits
TDO
290
ATmega128
2467L-AVR-05/04
ATmega128
Table 130. JTAG
1a.
a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 0110011_10000000 0100011_00010000 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0010111_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0100011_00000010 0000111_aaaaaaaa 0000011_bbbbbbbb 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00010001 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000011 0000111_aaaaaaaa TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (9) (1) (9) (9) (1) (9) (2)
1b. 2a. Flash 2b. 2c. 2d. 2e. 2f.
2g. Flash
(1)
2h. 3a. Flash 3b. 3c. 3d.
(2)
4a. EEPROM 4b. 4c. 4d. 4e.
4f. EEPROM
(1)
4g. 5a. EEPROM 5b.
(2)
291
2467L-AVR-05/04
Table 130. JTAG
5c. 5d.
a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0000011_bbbbbbbb 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_01000000 0010011_iiiiiiii 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 0110111_00000000 0010011_iiiiiiii 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0010011_iiiiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00100000 0010011_11iiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000100 0111010_00000000 0111011_00000000 0111110_00000000 0111111_00000000 0110010_00000000 0110011_00000000 0110110_00000000 0110111_00000000 TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) (4) (1) (3) (1)
6a. 6b.
(6)
6c.
6d. 6e. (7) 6f.
(2) (3) (1)
6g. 6h. 6i.
(7)
(2) (3) (1)
6j. 7a. 7b. 7c.
(9)
(2)
7d. 8a. / 8b. (6) 8c. (7) 8d. (8) 8e. (9)
(2)
292
ATmega128
2467L-AVR-05/04
ATmega128
Table 130. JTAG
8f. a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00001000 0000011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_00001000 0000011_bbbbbbbb 0110110_00000000 0110111_00000000 0100011_00000000 0110011_00000000 TDO xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (5) fuse ext. byte fuse high byte fuse low byte lock bits
9a. 9b. 9c. 10a. 10b. 10c. 11a. Notes:
1. ( ) 7 MSB 2. o = "1" 3. "0" = "1" = 4. "0" = "1" = 5. "0" = "1" = 6. P 269Table 117 7. P 270Table 118 8. P 270Table 119 9. P 268Table 115 10. PCMSB EEAMSB(Table 123 Table 124)
293
2467L-AVR-05/04
Figure 149. /
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
Flash
Flash Flash 8 Flash LSB MSB Flash
294
ATmega128
2467L-AVR-05/04
ATmega128
Figure 150. Flash
STROBES
TDI
State machine
ADDRESS
Flash EEPROM Fuses Lock Bits
D A T A
TDO
Flash
Flash Flash 8 8 Flash 8 LSB MSB Flash Figure 151. Flash
STROBES
TDI
State machine
ADDRESS
Flash EEPROM Fuses Lock Bits
D A T A
TDO

"1a" "1b" Table 130 1. JTAG AVR_RESET 1 Reset 2. PROG_ENABLE 1010_0011_0111_0000
1. JTAG PROG_COMMANDS 2. 11a 295
2467L-AVR-05/04
3. PROG_ENABLE 0000_0000_0000_0000 4. JTAG AVR_RESET 0 Reset 1. JTAG PROG_COMMANDS 2. 1a 3. 1b tWLRH_CE( P 280Table Note: ) Flash Flash P 296" " 1. JTAG PROG_COMMANDS 2. 2a Flash 3. 2b 4. 2c 5. 2d 2e 2f 6. 4 5 7. 2g 8. 2h Flash tWLRH( P 280Table Note: ) 9. 3 7 PROG_PAGELOAD 1. JTAG PROG_COMMANDS 2. 2a Flash 3. 2b 2c PCWORD( P 273Table 123 ) 0 4. JTAG PROG_PAGELOAD 5. LSB MSB 6. JTAG PROG_COMMANDS 7. 2g 8. 2hFlash tWLRH( P 280Table Note: ) 9. 3 8
296
ATmega128
2467L-AVR-05/04
ATmega128
Flash 1. JTAG PROG_COMMANDS 2. 3a Flash 3. 3b 3c 4. 3d 5. 3 4 PROG_PAGEREAD 1. JTAG PROG_COMMANDS 2. 3a Flash 3. 3b 3c PCWORD( P 273Table 123 ) 0 4. JTAG PROG_PAGEREAD 5. LSB MSB 6. JTAG PROG_COMMANDS 7. 3 6 EEPROM EEPROM P 296" " 1. JTAG PROG_COMMANDS 2. 4a EEPROM 3. 4b 4. 4c 5. 4d 4e 6. 4 5 7. 4f 8. 4gEEPROM tWLRH( P 280Table Note: ) 9. 3 8 EEPROM PROG_PAGELOAD EEPROM 1. JTAG PROG_COMMANDS 2. 5a EEPROM 3. 5b 5c 4. 5d 5. 3 4 EEPROM PROG_PAGEREAD
297
2467L-AVR-05/04
1. JTAG PROG_COMMANDS 2. 6a 3. 6b 0 4. 6c 5. 6d tWLRH( P 280Table Note: ) 6. 6e 0 1 7. 6f 8. 6g tWLRH( P 280Table Note: ) 9. 6h 0 1 10. 6i 11. 6j tWLRH( P 280Table Note: )
1. JTAG PROG_COMMANDS 2. 7a 3. 7b 0 4. 7c 5. 7d tWLRH( P 280Table Note: )
1. JTAG PROG_COMMANDS 2. 8a / 3. 8f 8b 8c 8d 8e
1. JTAG PROG_COMMANDS 2. 9a 3. 9b $00 4. 9c 5. $01 $02 3 4
1. JTAG PROG_COMMANDS 2. 10a 3. 10b $00 4. 10c
298
ATmega128
2467L-AVR-05/04
ATmega128
Note: AVR
*
........................................................ -55C +125C ........................................................ -65C +150C RESET ..................................................... -1.0V VCC+0.5V RESET ................... -1.0V +13.0V .................................................................... 6.0V I/O DC ......................................... 40.0 mA DC VCC GND ............................. 200.0 mA *NOTICE:
TA = -40C- 85C, VCC = 2.7V - 5.5V ( )
VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOH IIL IIH RRST RPEN RPU ( A,B,C,D, E, F, G)
(3)
XTAL1 RESET XTAL1 RESET XTAL1 RESET XTAL1 RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V Vcc = 5.5V, ( ) Vcc = 5.5V, ( )
-0.5 -0.5 -0.5 0.6 VCC(2) 0.7 VCC(2) 0.85 VCC(2)
0.3 VCC(1) 0.1 VCC(1) 0.2 VCC
(1)
V V V V V V V V V V
VCC + 0.5 VCC + 0.5 VCC + 0.5 0.7 0.5
( A,B,C,D) I/O I/O Reset PEN I/O
4.0 2.2 8.0 8.0 30 25 33 100 100 122
A A k k k
299
2467L-AVR-05/04
TA = -40C- 85C, VCC = 2.7V - 5.5V ( )
4 MHz, VCC = 3V (ATmega128L) 8 MHz, VCC = 5V (ATmega128) 4 MHz, VCC = 3V (ATmega128L) 8 MHz, VCC = 5V (ATmega128) (5) VACIO IACLK tACID Notes: WDT VCC = 3V WDT VCC = 3V VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 5.0V -50 750 500 < 25 < 10 5 20 2 12 40 25 40 50 mA mA mA mA A A mV nA ns
ICC
1. " " 2. " " 3. ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V TQFP 1] IOL 400 mA 2] A0 - A7, G2, C3 - C7 IOL 300 mA 3] C0 - C2, G0 - G1, D0 - D7, XTAL2 IOL 150 mA 4] B0 - B7, G3 - G4, E0 - E7 IOL 150 mA 5] F0 - F7 IOL 200 mA IOL VOL 4. ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V TQFP 1] IOH 400 mA 2] A0 - A7, G2, C3 - C7 IOL 300 mA 3] C0 - C2, G0 - G1, D0 - D7, XTAL2 IOL 150 mA 4] B0 - B7, G3 - G4, E0 - E7 IOL 150 mA 5] F0 - F7 IOL 200 mA IOH VOH
Figure 152.
V IH1 V IL1
300
ATmega128
2467L-AVR-05/04
ATmega128
Table 131.
VCC = 2.7V - 5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 125 50 50 1.6 1.6 2 8 VCC = 4.5V - 5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s %
tCLCL
Table 132. RC
R [k](1) 100 33 10 Notes: C [pF] 47 22 22 f(2) 87 kHz 650 kHz 2.0 MHz
1. R 3 k - 100 k 20 pF C C 2.
301
2467L-AVR-05/04
Table 133 ATmega128 Figure 153 Table 133.
VIL VIH Vhys(1) VOL tr(1) tof(1) tSP(1) Ii Ci(1) fSCL
(1)
SDA SCL VIHmin VILmax I/O I/O SCL
-0.5 0.7 VCC 0.05 VCC(2)
0.3 VCC VCC + 0.5 - 0.4
(3)(2) (3)(2)
V V V V ns ns ns A pF kHz s s s s s s s s s s ns ns s s s
3 mA
(3)
0 20 + 0.1Cb
300 250 50(2) 10 10 400 1000ns -----------------Cb 300ns --------------Cb - - - - - - - - 3.45 0.9 - - - - -
10 pF < Cb < 400 pF
20 + 0.1Cb 0 -10 -
0.1 VCC < Vi < 0.9 VCC fCK(4) > max(16fSCL, 250kHz)
(5)
0 V CC - 0,4V ----------------------------3mA V CC - 0,4V ----------------------------3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7
fSCL 100 kHz Rp fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz
(6) (7)
tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Notes: 1. 2. 3. 4.
START ( ) SCL SCL STARTS STOP STOP START
fSCL > 100 kHz fSCL 100 kHz
fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz
ATmega128 100% fSCL > 100 kHz Cb = fCK = CPU 5. ATmega128 fSCL
302
ATmega128
2467L-AVR-05/04
ATmega128
6. ATmega128 (1/fSCL - 2/fCK) fSCL = 100 kHz fCK 6 MHz 7. ATmega128 (1/fSCL - 2/fCK) fCK = 8 MHz fSCL > 308 kHz ATmega128 ATmega128 (400 kHz) tLOW
Figure 153.
tof tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tHIGH tLOW tr
tBUF
SPI
Figure 154 Figure 155 Table 134. SPI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note: SCK SCK / / SCK SCK SCK SS SCK SCK / / SCK SCK SS SS SS SCK 20 20 10 10 10 15 ns 4 * tck 2 * tck TBD s Table 72 50% TBD 10 10 0.5 * tsck 10 10 15 ns
1. SPI SCK - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK >12 MHz
303
2467L-AVR-05/04
Figure 154. SPI ( )
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
Figure 155. SPI ( )
18
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
304
ATmega128
2467L-AVR-05/04
ATmega128
Table 135. ADC
= 1x 20x = 200x VREF = 4V ADC = 200 kHz ADHSM = 0 VREF = 4V ADC = 1 MHz ADHSM = 1 ( ) VREF = 4V VREF = 4V VREF = 4V ADHSM = 0 ADHSM = 1 AVCC VREF VIN VINT RREF RAIN Notes: 1. 2. AVCC 2.7 V 3. AVCC 5.5 V 55 2.3 2.56 32 100 ADHSM = 0 ADHSM = 1 50 13 VCC - 0.3(2) 2.0 GND 1.5 3.25 (1) (1) (1) 10 Bits LSB LSB
1.5
LSB
3.75
LSB
0.75 0.5 1 1 1000 260 VCC + 0.3(3) AVCC VREF 38.5 2.7
LSB LSB LSB LSB kHz s V V V kHz V k M
305
2467L-AVR-05/04
Table 136. ADC
= 1x = 10x = 200x = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 10x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 200x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz (INL) ( ) = 10x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 200x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 1x = 10x = 200x = 1x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 10x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz = 200x VREF = 4V, VCC = 5V ADC = 50 - 200 kHz AVCC VREF VIN VDIFF ADC 50 65 VCC - 0.3 2.0 GND -VREF/Gain -511 4
(2)
(1)
(1)
(1) 10 10 10
Bits Bits Bits LSB
17
17
LSB
7
LSB
1.5
LSB
2
LSB
5 1.5 1.5 0.5 2
LSB % % % LSB
3
LSB
4 200 260 VCC + 0.3 VCC VREF/Gain 511
(3)
LSB kHz s V V V V LSB kHz
AVCC - 0.5
306
ATmega128
2467L-AVR-05/04
ATmega128
Table 136. ADC (Continued)
VINT RREF RAIN Notes: 1. 2. AVCC 2.7 V 3. AVCC 5.5 V 55 (1) 2.3 (1) 2.56 32 100 (1) 2.7 V k M
307
2467L-AVR-05/04
Table 137. 4.5 - 5.5V
8 MHz 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 13 14 15 16 Notes: 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH tDVWL tWHDX tDVWH tWLWH ALE ALE ALE C ALE RD WR ALE WR ALE RD RD RD RD WR WR WR WR 0 115 42.5 115 125 115 115 57.5 5 5 57.5 115 115 47.5 47.5 40 75 0 1.0tCLCL-10 0.5tCLCL-20 1.0tCLCL 1.0tCLCL-10
(1)
0.0 1.0tCLCL-10 0.5tCLCL-5(1) 5 5 0.5tCLCL-5
(1)
16
MHz ns ns ns ns ns ns ns
1.0tCLCL-10 1.0tCLCL-10 67.5 67.5 0.5tCLCL-15(2) 0.5tCLCL-15 40 1.0tCLCL-50
(2)
0.5tCLCL+5(2) 0.5tCLCL+5
(2)
ns ns ns ns ns ns ns ns ns ns
1.0tCLCL-10
1. 50% XTAL1 2. 50% XTAL1
Table 138. 4.5 - 5.5V
8 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 240 240 240 200 2.0tCLCL-10 2.0tCLCL 2.0tCLCL-10 0.0 16 2.0tCLCL-50 MHz ns ns ns ns
308
ATmega128
2467L-AVR-05/04
ATmega128
Table 139. 4.5 - 5.5V SRWn1 = 1 SRWn0 = 0
4 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 365 375 365 325 3.0tCLCL-10 3.0tCLCL 3.0tCLCL-10 0.0 16 3.0tCLCL-50 MHz ns ns ns ns
Table 140. 4.5 - 5.5V SRWn1 = 1 SRWn0 = 1
4 MHz 0 10 12 14 15 16 1/tCLCL tRLDV tRLRH tWHDX tDVWH tWLWH RD WR WR WR 365 240 375 365 325 3.0tCLCL-10 2.0tCLCL-10 3.0tCLCL 3.0tCLCL-10 0.0 16 3.0tCLCL-50 MHz ns ns ns ns ns
Table 141. 2.7 - 5.5V
4 MHz 0 1 2 3a 3b 4 5 6 7 8 9 10 11 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX ALE ALE A ALE ALE ALE C RD WR ALE WR ALE RD RD RD 0 235 115 5 5 115 235 235 115 115 45 190 0 130 130 0.0 tCLCL-15 0.5tCLCL-10(1) 5 5 0.5tCLCL-10
(1)
8 MHz ns ns ns ns ns ns ns 0.5tCLCL+5 0.5tCLCL+5
(2) (2)
1.0tCLCL-15 1.0tCLCL-15 0.5tCLCL-10 0.5tCLCL-10 45 1.0tCLCL-60
(2) (2)
ns ns ns ns ns
309
2467L-AVR-05/04
Table 141. 2.7 - 5.5V
4 MHz 12 13 14 15 16 Notes: tRLRH tDVWL tWHDX tDVWH tWLWH RD WR WR WR WR 235 105 235 250 235 1.0tCLCL-15 0.5tCLCL-20 1.0tCLCL 1.0tCLCL-15
(1)
ns ns ns ns ns
1.0tCLCL-15
1. 50% XTAL1 2. 50% XTAL1
Table 142. 2.7 - 5.5 V SRWn1 = 0 SRWn0 = 1
4 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 485 500 485 440 2.0tCLCL-15 2.0tCLCL 2.0tCLCL-15 0.0 8 2.0tCLCL-60 MHz ns ns ns ns
Table 143. 2.7 - 5.5 V SRWn1 = 1 SRWn0 = 0
4 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 735 750 735 690 3.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 0.0 8 3.0tCLCL-60 Unit MHz ns ns ns ns
Table 144. 2.7 - 5.5 V SRWn1 = 1 SRWn0 = 1
4 MHz 0 10 12 14 15 16 1/tCLCL tRLDV tRLRH tWHDX tDVWH tWLWH RD WR WR WR 735 485 750 735 690 3.0tCLCL-15 2.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 0.0 8 3.0tCLCL-60 MHz ns ns ns ns ns
310
ATmega128
2467L-AVR-05/04
ATmega128
Figure 156. (SRWn1 = 0, SRWn0 = 0
T1 T2 T3 T4
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
Figure 157. (SRWn1 = 0, SRWn0 = 1)
T1 T2 T3 T4 T5
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
311
2467L-AVR-05/04
Read
Write
DA7:0
Prev. data
Address
Data
Read
Write
DA7:0
Prev. data
Address
Data
Figure 158. (SRWn1 = 1, SRWn0 = 0)
T1 T2 T3 T4 T5 T6
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
Figure 159. (SRWn1 = 1, SRWn0 = 1)(1)
T1 T2 T3 T4 T5 T6 T7
System Clock (CLKCPU )
1
ALE
4 7 Address 15 2 3a XX 13
A15:8
Prev. addr.
6
16
14
WR
3b 9 Data 10 8 12 11
DA7:0 (XMBK = 0)
Address 5
RD
Note:
1. (T4-T7) ALE RAM ( )
312
ATmega128
2467L-AVR-05/04
Read
Write
DA7:0
Prev. data
Address
Data
Read
Write
DA7:0
Prev. data
Address
Data
ATmega128
ATmega128
I/O I/O CL*VCC*f CL VCC f Figure 160. (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
3.5 3 2.5 2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V
ICC (mA)
Frequency (MHz)
313
2467L-AVR-05/04
Figure 161. (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 45 40 35 30
5.0 V 4.5 V
ICC (mA)
25 20 15 10 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
4.0 V 3.6 V 3.3 V 3.0 V 2.7 V
Figure 162. VCC ( RC 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
4
3.5
25 C -40 C 85 C
ICC (mA)
3
2.5
2
1.5 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
314
ATmega128
2467L-AVR-05/04
ATmega128
Figure 163. VCC ( RC 2 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 2 MHz 8 7 6 5
-40 C 25 C 85 C
ICC (mA)
4 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 164. VCC ( RC 4 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4 MHz 14 12
-40 C 25 C 85 C
10 8 6 4
ICC (mA)
2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
315
2467L-AVR-05/04
Figure 165. VCC ( RC 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 25
20
-40 C 25 C 85 C
15
ICC (mA)
10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 166. VCC (32 kHz )
ACTIVE SUPPLY CURRENT vs. VCC
32 kHz EXTERNAL OSCILLATOR 140
120
25 C
100
ICC (uA)
80
60
40
20
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
316
ATmega128
2467L-AVR-05/04
ATmega128
Figure 167. (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz)
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 3.0 V 2.7 V
Figure 168. (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
ICC (mA)
25
5.5 V
20
5.0 V 4.5 V
15
ICC (mA)
4.0 V
10
3.6 V
5
3.3 V 3.0 V 2.7 V
0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
317
2467L-AVR-05/04
Figure 169. VCC ( RC 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz 1.6 1.4 1.2 1
85 C 25 C -40 C
ICC (mA)
0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 170. VCC ( RC 2 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 2 MHz 3
2.5
85 C 25 C -40 C
2
ICC (mA)
1.5
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
318
ATmega128
2467L-AVR-05/04
ATmega128
Figure 171. VCC ( RC 4 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4 MHz 6
-40 C 25 C 85 C
5
4
ICC (mA)
3
2
1
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 172. VCC ( RC 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 12
10
-40 C 25 C 85 C
8
ICC (mA)
6
4
2
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
319
2467L-AVR-05/04
Figure 173. VCC (32 kHz )
IDLE SUPPLY CURRENT vs. VCC
32 kHz EXTERNAL OSCILLATOR 60
50
25 C
40
ICC (uA)
30
20
10
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 174. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED 4.5 4 3.5 3
ICC (uA)
85 C
2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40 C 25 C
320
ATmega128
2467L-AVR-05/04
ATmega128
Figure 175. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED 35 30 25
ICC (uA)
85 C 25 C -40 C
20 15 10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 176. VCC ( )
POWER-SAVE SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED 16
25 C
14 12 10
ICC (uA)
8 6 4 2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
321
2467L-AVR-05/04
Standby
Figure 177. Standby VCC,
STANDBY SUPPLY CURRENT vs. VCC
0.2 0.18 0.16 0.14 0.12
6 MHz Xtal 6 MHz Res
4 MHz Res 4 MHz Xtal
ICC (mA)
0.1 0.08 0.06 0.04 0.02 0 2.5 3 3.5 4 4.5 5
2 MHz Res 2 MHz Xtal 455 kHz Res 1 MHz Res
5.5
VCC (V)
Figure 178. Standby VCC, (CKOPT )
STANDBY SUPPLY CURRENT vs. VCC
CKOPT programmed 2.5
16 MHz Xtal
2
12 MHz Xtal
1.5
ICC (mA)
6 MHz Xtal 4 MHz Xtal
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
322
ATmega128
2467L-AVR-05/04
ATmega128
Figure 179. I/O (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V 160 140
85 C
120
25 C -40 C
100
IOP (uA)
80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5
Figure 180. I/O (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V 80
85 C 25 C
70 60 50
-40 C
IOP (uA)
40 30 20 10 0 0 0.5 1 1.5 VOP (V) 2 2.5 3
323
2467L-AVR-05/04
Figure 181. I/O (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V 90 80 70 60
-40 C 25 C 85 C
IOH (mA)
50 40 30 20 10 0 2.5 3 3.5 VOH (V) 4 4.5 5
Figure 182. I/O (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V 30
-40 C
25
25 C 85 C
20
IOH (mA)
15
10
5
0 0.5 1 1.5 VOH (V) 2 2.5 3
324
ATmega128
2467L-AVR-05/04
ATmega128
Figure 183. I/O (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V 90 80 70 60
-40 C 25 C 85 C
IOL (mA)
50 40 30 20 10 0 0 0.5 1 VOL (V) 1.5 2 2.5
Figure 184. I/O VCC = 2.7V
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V 35
-40 C
30
25
25 C 85 C
IOL (mA)
20
15
10
5
0 0 0.5 1 VOL (V) 1.5 2 2.5
325
2467L-AVR-05/04
Figure 185. I/O VCC (VIH I/O `1')
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1' 2.2
2
-40 C 25 C 85 C
1.8
Threshold (V)
1.6
1.4
1.2
1 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 186. I/O VCC (VIH I/O `0')
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0' 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40 C 25 C 85 C
326
ATmega128
2467L-AVR-05/04
Threshold (V)
ATmega128
Figure 187. I/O VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.7
0.6
85 C 25 C -40 C
0.5
Input Hysteresis (V)
0.4
0.3
0.2
0.1
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
BOD
Figure 188. BOD (BODLEVEL 4.0V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 4.0 V 4.4
4.2
Rising VCC
Threshold (V)
4
Falling VCC
3.8
3.6
3.4 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
327
2467L-AVR-05/04
Figure 189. BOD (BODLEVEL 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 2.7 V 3
2.8
Rising VCC
Threshold (V)
2.6
Falling VCC
2.4
2.2
2 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Figure 190.
BANDGAP VOLTAGE vs. VCC
1.275
1.27
85 C -40 C
Bandgap Voltage (V)
1.265
25 C
1.26
1.255
1.25 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
328
ATmega128
2467L-AVR-05/04
ATmega128
Figure 191. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
1220 1200 1180 1160
-40 C 25 C 85 C
FRC (kHz)
1140 1120 1100 1080 1060 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 192. 1 MHz RC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1.02
1
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V
0.98
FRC (MHz)
0.96
0.94
0.92
0.9 -60 -40 -20 0 20 Temperature 40 60 80 100
329
2467L-AVR-05/04
Figure 193. 1 MHz RC VCC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. Vcc
1.02
1
-40 C 25 C 85 C
0.98
FRC (MHz)
0.96
0.94
0.92
0.9 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 194. 1 MHz RC Osccal
1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
1.5 1.4 1.3 1.2 1.1
FRC (MHz)
25 C
1 0.9 0.8 0.7 0.6 0.5 0.4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE
330
ATmega128
2467L-AVR-05/04
ATmega128
Figure 195. 2 MHz RC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
2.05
2
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V
1.95
FRC (MHz)
1.9
1.85
1.8
1.75 -60 -40 -20 0 20 Temperature 40 60 80 100
Figure 196. 2 MHz RC VCC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. Vcc
2.05
-40 C 25 C
2
85 C
FRC (MHz)
1.95
1.9
1.85
1.8 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
331
2467L-AVR-05/04
Figure 197. 2 MHz RC Osccal
2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
4 3.5 3 2.5 2 1.5 1 0.5 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE
25 C
Figure 198. 4 MHz RC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
4.1 4.05 4 3.95
FRC (MHz)
FRC (MHz)
3.9 3.85 3.8 3.75 3.7 3.65 3.6 -60 -40 -20 0 20 Temperature 40 60 80 100
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V
2.7 V
332
ATmega128
2467L-AVR-05/04
ATmega128
Figure 199. 4 MHz RC VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc
4.1 4.05 4 3.95
-40 C 25 C 85 C
FRC (MHz)
3.9 3.85 3.8 3.75 3.7 3.65 3.6 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 200. 4 MHz RC Osccal
4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
9 8 7 6
FRC (MHz)
25 C
5 4 3 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
333
2467L-AVR-05/04
Figure 201. 8 MHz RC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.4 8.2 8 7.8
FRC (MHz)
5.5 V 5.0 V 4.5 V
7.6 7.4 7.2 7 6.8 6.6 -60 -40 -20 0 20 Temperature 40 60 80 100
4.0 V 3.6 V 3.3 V 2.7 V
Figure 202. 8 MHz RC VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc
8.4 8.2 8 7.8
-40 C 25 C 85 C
FRC (MHz)
7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
334
ATmega128
2467L-AVR-05/04
ATmega128
Figure 203. 8 MHz RC Osccal
8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
16
25 C
14 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE
Figure 204. BOD VCC
BROWNOUT DETECTOR CURRENT vs. VCC
25
FRC (MHz)
20
-40 C 25 C 85 C
15
ICC (uA)
10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
335
2467L-AVR-05/04
Figure 205. ADC VCC (ADC 50 kHz
ADC CURRENT vs. VCC
ADC AT 50KHz 600
500
-40 C 25 C 85 C
400
ICC (uA)
300
200
100
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 206. ADC VCC (ADC 1 MHz)
AREF CURRENT vs. VCC
ADC AT 1MHz 250
200
25 C 85 C -40 C
150
ICC (uA)
100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
336
ATmega128
2467L-AVR-05/04
ATmega128
Figure 207. VCC
ANALOG COMPARATOR CURRENT vs. VCC
100 90 80 70 60
85 C 25 C -40 C
ICC (uA)
50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 208. VCC
PROGRAMMING CURRENT vs. VCC
9 8 7 6
-40 C
25 C 85 C
ICC (mA)
5 4 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
337
2467L-AVR-05/04
Figure 209. VCC (0.1 - 1.0 MHz )
RESET SUPPLY CURRENT vs. VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP 4.5 4 3.5 3
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 3.0 V 2.7 V
ICC (mA)
2.5 2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz)
Figure 210. VCC (1 - 20MHz )
RESET SUPPLY CURRENT vs. VCC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 40 35 30 25
5.5 V 5.0 V 4.5 V 4.0 V
ICC (mA)
20 15 10 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
3.6 V 3.3 V 3.0 V 2.7 V
338
ATmega128
2467L-AVR-05/04
ATmega128
Figure 211. (VCC = 5.0V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V 120
-40 C
100
25 C 85 C
80
IRESET (uA)
60
40
20
0 0 1 2 3 VRESET (V) 4 5 6
Figure 212. (VCC = 2.7V
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 2.7V 60
-40 C
50
25 C 85 C
40
IRESET (uA)
30
20
10
0 0 0.5 1 1.5 VRESET (V) 2 2.5 3
339
2467L-AVR-05/04
Figure 213. VCC (VIH `1')
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1' 2.5
2
-40 C
Threshold (V)
1.5
25 C 85 C
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 214. VCC (VIH `0')
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0' 2.5
-40 C 25 C 85 C
2
Threshold (V)
1.5
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
340
ATmega128
2467L-AVR-05/04
ATmega128
Figure 215. VCC
RESET INPUT PIN HYSTERESIS vs. VCC
0.5 0.45 0.4
-40 C
Input Hysteresis (mV)
0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
25 C
85 C
Figure 216. VCC ( 1 MHz)
RESET PULSE WIDTH vs. VCC
External Clock, 1 MHz 1.2
1
Pulsewidth (us)
0.8
0.6
0.4
85 C 25 C -40 C
0.2
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
341
2467L-AVR-05/04
($FF) .. ($9E) ($9D) ($9C) ($9B) ($9A) ($99) ($98) ($97) ($96) ($95) ($94) ($93) ($92) ($91) ($90) ($8F) ($8E) ($8D) ($8C) ($8B) ($8A) ($89) ($88) ($87) ($86) ($85) ($84) ($83) ($82) ($81) ($80) ($7F) ($7E) ($7D) ($7C) ($7B) ($7A) ($79) ($78) ($77) ($76) ($75) ($74) ($73) ($72) ($71) ($70) ($6F) ($6E) ($6D) ($6C) ($6B) ($6A) ($69) ($68) ($67) ($66) ($65) ($64) ($63) ($62)
UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H UCSR0C UBRR0H TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L ETIMSK ETIFR TCCR1C OCR1CH OCR1CL TWCR TWDR TWAR TWSR TWBR OSCCAL XMCRA XMCRB EICRA SPMCSR PORTG DDRG PING PORTF
Bit 7
- - - - RXC1 RXCIE1 - - - - - - - - - - - - FOC3A COM3A1 ICNC3
Bit 6
- - - UMSEL1 TXC1 TXCIE1 - - - UMSEL0 - - - - - - - - FOC3B COM3A0 ICES3
Bit 5
- - - UPM11 UDRE1 UDRIE1 - - - UPM01 - - - - - - - - FOC3C COM3B1 -
Bit 4
- - - UPM10 FE1 RXEN1 - - - UPM00 - - - - - - - - - COM3B0 WGM33
Bit 3
- - - USBS1 DOR1 TXEN1
Bit 2
- - - UCSZ11 UPE1 UCSZ12
Bit 1
- - - UCSZ10 U2X1 RXB81
Bit 0
- - - UCPOL1 MPCM1 TXB81
174 173 173 174 176 176
USART1 I/O
USART1 USART1 - - USBS0 - - - - - - - - COM3C1 WGM32 - - UCSZ01 - - - - - - - - COM3C0 CS32 - - UCSZ00 - - - - - - - - WGM31 CS31 - - UCPOL0 - - - -
174
USART0 - - - - WGM30 CS30
176
124 120 123 125 125 125 125 125 125 126 125 126 126
T/C3 - T/C3 - T/C3 - A T/C3 - A T/C3 - B T/C3 - B T/C3- C T/C3 - C T/C3 - T/C3 - - - - - - FOC1A - - - - - FOC1B - - TICIE3 ICF3 - FOC1C - - OCIE3A OCF3A - - - - OCIE3B OCF3B - - - - TOIE3 TOV3 - - - - OCIE3C OCF3C - - - - OCIE1C OCF1C - -
127 128 124 125 125
T/C1 - C T/C1 - C - - - TWINT TWA6 TWS7 - - - TWEA TWA5 TWS6 - - - TWSTA TWA4 TWS5 - - - TWSTO TWA3 TWS4 - - - TWWC TWA2 TWS3 - - - TWEN TWA1 - - - - - TWA0 TWPS1 - - - TWIE TWGCE TWPS0
188 189 190 189 188 38
- - XMBK - ISC31 - SPMIE - - - - - PORTF7 - SRL2 - - ISC30 - RWWSB - - - - - PORTF6 - SRL1 - - ISC21 - - - - - - - PORTF5 - SRL0 - - ISC20 - RWWSRE - - PORTG4 DDG4 PING4 PORTF4 - SRW01 - - ISC11 - BLBSET - - PORTG3 DDG3 PING3 PORTF3 - SRW00 XMM2 - ISC10 - PGWRT - - PORTG2 DDG2 PING2 PORTF2 - SRW11 XMM1 - ISC01 - PGERS - - PORTG1 DDG1 PING1 PORTF1 XMM0 - ISC00 - SPMEN - - PORTG0 DDG0 PING0 PORTF0 -
28 29 84 258
83 83 83 82
342
ATmega128
2467L-AVR-05/04
ATmega128
($61) ($60) $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22)
DDRF Reserved SREG SPH SPL XDIV RAMPZ EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE DDRE
Bit 7
DDF7 - I SP15 SP7 XDIVEN - ISC71 INT7 INTF7 OCIE2 OCF2 SRE JTD FOC0
Bit 6
DDF6 - T SP14 SP6 XDIV6 - ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 - WGM00
Bit 5
DDF5 - H SP13 SP5 XDIV5 - ISC61 INT5 INTF5 TICIE1 ICF1 SE - COM01
Bit 4
DDF4 - S SP12 SP4 XDIV4 - ISC60 INT4 INTF4 OCIE1A OCF1A SM1 JTRF COM00
Bit 3
DDF3 - V SP11 SP3 XDIV3 - ISC51 INT3 INTF3 OCIE1B OCF1B SM0 WDRF WGM01 T/C0 (8 )
Bit 2
DDF2 - N SP10 SP2 XDIV2 - ISC50 INT2 INTF TOIE1 TOV1 SM2 BORF CS02
Bit 1
DDF1 - Z SP9 SP1 XDIV1 - ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01
Bit 0
DDF0 - C SP8 SP0 XDIV0 RAMPZ0 ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00
83 8 11 11 40 11 84 85 85 98, 126, 144 98, 128, 144 28, 41, 58 50, 237 94 96 96
T/C0 - COM1A1 ICNC1 - COM1A0 ICES1 - COM1B1 - - COM1B0 WGM13 AS0 COM1C1 WGM12 TCN0UB COM1C0 CS12 OCR0UB WGM11 CS11 TCR0UB WGM10 CS10
97 120 123 125 125 125 125 125 125 126 126
T/C1 - T/C1 - T/C1 - A T/C1 - A T/C1 - B T/C1 - B T/C1 - T/C1 - FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 T/C2 (8 ) T/C2
IDRD/OCDR7
142 144 144
OCDR6 - - -
OCDR5 - - -
OCDR4 WDCE - -
OCDR3 WDE ACME
OCDR2 WDP2 PUD
OCDR1 WDP1 PSR0
OCDR0 WDP0 PSR321
234 52 68, 99, 131, 210 18 18 18
- TSM -
EEPROM
EEPROM EEPROM - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD REFS1 ADEN - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG REFS0 ADSC - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - DORD UDRE0 UDRIE0 ACO ADLAR ADFR - PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 - MSTR FE0 RXEN0 ACI MUX4 ADIF EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL DOR0 TXEN0 ACIE MUX3 ADIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA UPE0 UCSZ02 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 U2X0 RXB80 ACIS1 MUX1 ADPS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 MUX0 ADPS0
19 81 81 81 81 81 81 81 81 82 82 82 82 153 153 151 173 173 174 176 210 225 227 228 228
SPI
USART0 I/O
USART0
ADC ADC PORTE7 DDE7 PORTE6 DDE6 PORTE5 DDE5 PORTE4 DDE4 PORTE3 DDE3 PORTE2 DDE2 PORTE1 DDE1 PORTE0 DDE0
82 82
343
2467L-AVR-05/04
$01 ($21) $00 ($20)
PINE PINF
Bit 7
PINE7 PINF7
Bit 6
PINE6 PINF6
Bit 5
PINE5 PINF5
Bit 4
PINE4 PINF4
Bit 3
PINE3 PINF3
Bit 2
PINE2 PINF2
Bit 1
PINE1 PINF1
Bit 0
PINE0 PINF0
82 83
Notes:
1. 0 I/O 2. 1 CBISBII/O 1 CBI SBI $00 $1F
344
ATmega128
2467L-AVR-05/04
ATmega128
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k k (Z) (Z) I/O I/O / 0 T T PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 I Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr 1 2 0 Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C

ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC
1 1 R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) <<
R1:R0 (Rd x Rr) <<
345
2467L-AVR-05/04
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM ELPM ELPM ELPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b I/O I/O 4 4 T T 0 0 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V SREG(s) SREG(s) T C C N N Z Z I I S S Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr . SRAM SRAM Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 R0 (RAMPZ:Z) Rd (RAMPZ:Z) Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK
k k

if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1

BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM ELPM ELPM ELPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS
346
ATmega128
2467L-AVR-05/04
ATmega128
SEV CLV SET CLT SEH CLH MCU NOP SLEEP WDR BREAK Break ( ) ( )
2 2 SREG T SREG T SREG SREG
V1 V0 T1 T0 H1 H0
V V T T H H
SEV CLV SET CLT SEH CLH MCU NOP SLEEP WDR BREAK
347
2467L-AVR-05/04
(MHz) ATmega128L-8AC ATmega128L-8MC 8 2.7 - 5.5V ATmega128L-8AI ATmega128L-8AJ(2) ATmega128L-8MI ATmega128L-8MJ(2) ATmega128-16AC ATmega128-16MC 16 4.5 - 5.5V ATmega128-16AI ATmega128-16AJ(2) ATmega128-16MI ATmega128-16MJ(2) 64A 64M1 64A 64A 64M1 64M1 64A 64M1 64A 64A 64M1 64M1 (0oC - 70oC) (-40oC - 85oC)
(0oC - 70oC) (-40oC - 85oC)
Notes:
1. wafer Atmel 2.
64A 64M1 64- (1.0 mm) TQFP 64- 9 x 9 x 1.0 mm 0.50 mm MLF
348
ATmega128
2467L-AVR-05/04
ATmega128
64A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. B
R
349
2467L-AVR-05/04
64M1
D
Marked Pin# 1 ID
E
C
TOP VIEW
SEATING PLANE
A1 A 0.08 C
L D2
Pin #1 Corner
SIDE VIEW
1 2 3
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 b D D2 5.20 MIN 0.80 - 0.23 NOM 0.90 0.02 0.25 9.00 BSC 5.40 9.00 BSC 5.20 5.40 0.50 BSC 0.35 0.40 0.45 5.60 5.60 MAX 1.00 0.05 0.28 NOTE
E2
b
BOTTOM VIEW
e
E E2 e L
Notes: 1. JEDEC Standard MO-220, Fig. 1, VMMD.
01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. C
R
350
ATmega128
2467L-AVR-05/04
ATmega128
ATmega128 Rev. I
ATmega128 * XDIV * OSCCAL 1. XDIV XDIV 2% NOP 8 NOP 1.SREG I 2. XDIV 3. 8 NOP 4.SREG I
CLI OUT NOP NOP NOP NOP NOP NOP NOP NOP SEI XDIV, temp ; ; ; ; ; ; ; ; ; ; ;
2. OSCCAL OSCCAL 2% 1 JTAG IDCODE IDCODE TDI JTAG IDCODE IEEE1149.1 "1" TDI ID 1 Update-DR 1 ATmega128 IDCODE TAP Test-Logic-Reset ID ATmega128 ID ATmega128 BYPASS ID ATmega128 IDCODE TAP Test-Logic-Reset 351
2467L-AVR-05/04
ID ATmega128 IDCODE JTAG Update-DR ID
ATmega128 Rev. H
* XDIV * OSCCAL 1. XDIV XDIV 2% NOP 8 NOP 1.SREG I 2. XDIV 3. 8 NOP 4.SREG I
CLI OUT NOP NOP NOP NOP NOP NOP NOP NOP SEI XDIV, temp ; ; ; ; ; ; ; ; ; ; ;
2. OSCCAL OSCCAL 2% 1 JTAG IDCODE IDCODE TDI JTAG IDCODE IEEE1149.1 "1" TDI ID 1 Update-DR 1 ATmega128 352
ATmega128
2467L-AVR-05/04
ATmega128
IDCODE TAP Test-Logic-Reset ID ATmega128 ID ATmega128 BYPASS ID ATmega128 IDCODE TAP Test-Logic-Reset ID ATmega128 IDCODE JTAG Update-DR ID
ATmega128 Rev. G
* XDIV * OSCCAL 1. XDIV XDIV 2% NOP 8 NOP 1.SREG I 2. XDIV 3. 8 NOP 4.SREG I
CLI OUT NOP NOP NOP NOP NOP NOP NOP NOP SEI XDIV, temp ; ; ; ; ; ; ; ; ; ; ;
2. OSCCAL OSCCAL 2% 1 JTAG IDCODE IDCODE TDI
353
2467L-AVR-05/04
JTAG IDCODE IEEE1149.1 "1" TDI ID 1 Update-DR 1 ATmega128 IDCODE TAP Test-Logic-Reset ID ATmega128 ID ATmega128 BYPASS ID ATmega128 IDCODE TAP Test-Logic-Reset ID ATmega128 IDCODE JTAG Update-DR ID
ATmega128 Rev. F
* XDIV * OSCCAL 1. XDIV XDIV 2% NOP 8 NOP 1.SREG I 2. XDIV 3. 8 NOP 4.SREG I
CLI OUT NOP NOP NOP NOP NOP NOP NOP NOP SEI XDIV, temp ; ; ; ; ; ; ; ; ; ; ;
2. OSCCAL OSCCAL 2%
354
ATmega128
2467L-AVR-05/04
ATmega128
1 JTAG IDCODE IDCODE TDI JTAG IDCODE IEEE1149.1 "1" TDI ID 1 Update-DR 1 ATmega128 IDCODE TAP Test-Logic-Reset ID ATmega128 ID ATmega128 BYPASS ID ATmega128 IDCODE TAP Test-Logic-Reset ID ATmega128 IDCODE JTAG Update-DR ID
355
2467L-AVR-05/04
ATmega128
Rev. 2467K-03/04 Rev.2467L-05/04
1. " " "TBD" ICPx ICx 2. P 35Table 8 , P 47Table 19 , P 53Table 22 , P 226Table 96 , P 280Table 126 , P 284Table 128 , P 301Table 132 P 303Table 134 3. P 23" " 4. P 236" " 5. P 299" " 6. P 305" " 7. P 313"ATmega128 " 8. P 348" "
Rev. 2467J-12/03 Rev.2467K-03/04 Rev. 2467I-09/03 Rev.2467J-12/03 Rev. 2467H-02/03 Rev. 2467I-09/03
1. P 351" "
1. P 38" RC "
1. P 40"XTAL XDIV" 2. P 45"JTAG " 3. P 47Table 19 VBOT (BODLEVEL = 1) 4. P 229" TAP" JTAGEN 5. JTD 6. P 270Table 118 JTAGEN 7. P 299" " RPU 8. P 351" " IDCODE
Rev. 2467G-09/02 Rev. 2467H-02/03
1. SFIOR 2. P 296" Flash " P 297" EEPROM " 3. " " "32 kHz "
356
ATmega128
2467L-AVR-05/04
ATmega128
4. P 113Figure 52 OCn 5. 1 6. 0 2 PWM 7. TWI 8. Added reference to P 273Table 124 SPIFlash 9. P 261"()" SPMEEPROM
10. ADHSM 11. P 22" EEPROM " 12. P 349" "
Rev. 2467F-09/02 Rev. 2467G-09/02 Rev. 2467E-04/02 Rev. 2467F-09/02
1. Flash 10,000 /
1. 64 MLF P 348" " 2. P 30" ( 64KB)" 3. P 34" " 4. SPMCSR SPMCSR 5. P 39" " P 301Table 131, " ," 6. P 44" " OCD 7. (WGM ): P 90" PWM " (T/C0) P 92" PWM " (T/C0) P 136" PWM " (T/C2) P 138" PWM " (T/C2) 8. P 176Table 81 (USART) 9. P 243Table 102 ( ) 10. P 299" " Vil
Rev. 2467D-03/02 Rev. 2467E-04/02
1. P 313"ATmega128 " 2. :
357
2467L-AVR-05/04
P 47Table 19 P 51Table 20 P 143Table 68 P 243Table 102 Table 136 on page 328 3. OSCCAL 2 4 8 MHz P 38" OSCCAL" P 270" "
Rev. 2467C-02/02 Rev. 2467D-03/02
1. P 4"ATmega103 " 2. P 20Table 2, "EEPROM ," 3. P 34Table 7 , Table 9 P 36Table 10 , P 37Table 12 , P 38Table 14 P 39Table 16 4. P 53Table 22 WDT 5. P 227"ADC A ADCSRA" ADSC 6. P 224"ADC " ADC 7. JTAG 8. P 260"Flash" , P 261"SPM" P 261" " SPM( RAMPZ)
9. P 270Table 118 OCDEN 10. P 272Figure 135 P 282Figure 144 AVCC P 278Figure 139 11. PROG_PAGELOAD PROG_PAGEREAD 12. P 313"ATmega128 " RC 13. " TWI" TWI TWBRR TWI P 186" " P 187" " 14. P 40"XTAL XDIV" T/C0
Rev. 2467B-09/01 Rev. 2467C-02/02
1. G P 79" G " TOSC1 TOSC2 2. rev. F rev. G JTAG Table 100 3 TBD P 47Table 19 P 51Table 20 P 299" " P 301Table 131 P 303Table 134 Table 136
358
ATmega128
2467L-AVR-05/04
ATmega128
4. P 348" " 5. P 313"ATmega128 " 6. JTAG P 295 " " 7. JTAG P 298" " P 298" "
359
2467L-AVR-05/04
Atmel Corporation
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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2467L-AVR-05/04

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